Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module User's Guide

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2.16.1.2 Transmit Packet Completion Interrupts
2.16.1.3 Receive Packet Completion Interrupts
Architecture
The transmit DMA engine has eight channels, with each channel having a corresponding interrupt
(TXPEND n). The transmit interrupts are level interrupts that remain asserted until cleared by the CPU.
Each of the eight transmit channel interrupts may be individually enabled by setting the corresponding
bit in the transmit interrupt mask set register (TXINTMASKSET) to 1. Each of the eight transmit channel
interrupts may be individually disabled by clearing the corresponding bit in the transmit interrupt mask
clear register (TXINTMASKCLEAR) to 0. The raw and masked transmit interrupt status may be read
from the transmit interrupt status (unmasked) register (TXINTSTATRAW) and the transmit interrupt
status (masked) register (TXINTSTATMASKED), respectively.
When the EMAC completes the transmission of a packet, the EMAC issues an interrupt to the CPU by
writing the packet’s last buffer descriptor address to the appropriate channel queue’s transmit
completion pointer located in the state RAM block. The interrupt is generated by the write when
enabled by the interrupt mask, regardless of the value written.
Upon interrupt reception, the CPU processes one or more packets from the buffer chain and then
acknowledges an interrupt by writing the address of the last buffer descriptor processed to the queue’s
associated transmit completion pointer in the transmit DMA state RAM.
The data written by the host (buffer descriptor address of the last processed buffer) is compared to the
data in the register written by the EMAC port (address of last buffer descriptor used by the EMAC). If
the two values are not equal (which means that the EMAC has transmitted more packets than the CPU
has processed interrupts for), the transmit packet completion interrupt signal remains asserted. If the
two values are equal (which means that the host has processed all packets that the EMAC has
transferred), the pending interrupt is cleared. The value that the EMAC is expecting is found by reading
the transmit channel n completion pointer register (TX nCP).
The EMAC write to the completion pointer actually stores the value in the state RAM. The CPU written
value does not actually change the register value. The host written value is compared to the register
content (which was written by the EMAC) and if the two values are equal then the interrupt is removed;
otherwise, the interrupt remains asserted. The host may process multiple packets prior to
acknowledging an interrupt, or the host may acknowledge interrupts for every packet.
The receive DMA engine has eight channels, which each channel having a corresponding interrupt
(RXPEND n). The receive interrupts are level interrupts that remain asserted until cleared by the CPU.
Each of the eight receive channel interrupts may be individually enabled by setting the corresponding
bit in the receive interrupt mask set register (RXINTMASKSET) to 1. Each of the eight receive channel
interrupts may be individually disabled by clearing the corresponding bit in the receive interrupt mask
clear register (RXINTMASKCLEAR) to 0. The raw and masked receive interrupt status may be read
from the receive interrupt status (unmasked) register (RXINTSTATRAW) and the receive interrupt
status (masked) register (RXINTSTATMASKED), respectively.
When the EMAC completes a packet reception, the EMAC issues an interrupt to the CPU by writing the
packet's last buffer descriptor address to the appropriate channel queue's receive completion pointer
located in the state RAM block. The interrupt is generated by the write when enabled by the interrupt
mask, regardless of the value written.
Upon interrupt reception, the CPU processes one or more packets from the buffer chain and then
acknowledges one or more interrupt(s) by writing the address of the last buffer descriptor processed to
the queue's associated receive completion pointer in the receive DMA state RAM.
The data written by the host (buffer descriptor address of the last processed buffer) is compared to the
data in the register written by the EMAC (address of last buffer descriptor used by the EMAC). If the
two values are not equal (which means that the EMAC has received more packets than the CPU has
processed interrupts for), the receive packet completion interrupt signal remains asserted. If the two
values are equal (which means that the host has processed all packets that the EMAC has received),
the pending interrupt is de-asserted. The value that the EMAC is expecting is found by reading the
receive channel n completion pointer register (RX nCP).
SPRUEQ6 – December 2007 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) 57
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