Video Port/VCXO Interpolated Control (VIC) Port User's Guide

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4.12.2 Video Display Control Register (VDCTL)
Video Display Registers
Figure 4-31. Video Display Status Register (VDSTAT)
31 30 29 28 27 16
Reserved FRMD F2D F1D VDYPOS
R-0 R/WC-0 R/WC-0 R/WC-0 R-0
15 14 13 12 11 0
Reserved VBLNK VDFLD VDXPOS
R-0 R-0 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 4-6. Video Display Status Register (VDSTAT) Field Descriptions
Bit field
(1)
symval
(1)
Value Description
31 Reserved - 0 Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
30 FRMD OF( value) Frame displayed bit. Write 1 to clear the bit, a write of 0 has no effect.
DEFAULT 0 Complete frame has not been displayed.
NONE
DISPLAYED 1 Complete frame has been displayed.
CLEAR
29 F2D OF( value) Field 2 displayed bit. Write 1 to clear the bit, a write of 0 has no effect.
DEFAULT 0 Field 2 has not been displayed.
NONE
DISPLAYED 1 Field 2 has been displayed.
CLEAR
28 F1D OF( value) Field 1 displayed bit. Write 1 to clear the bit, a write of 0 has no effect.
DEFAULT 0 Field 1 has not been displayed.
NONE
DISPLAYED 1 Field 1 has been displayed.
CLEAR
27-16 VDYPOS OF( value) 0-FFFh Current frame line counter (FLCOUNT) value. Index of the current line in the current
field being displayed by the module.
DEFAULT 0
15-14 Reserved - 0 Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
13 VBLNK OF( value) Vertical blanking bit.
DEFAULT 0 Video display is not in a vertical-blanking interval.
EMPTY
NOTEMPTY 1 Video display is in a vertical-blanking interval.
12 VDFLD OF( value) VDFLD bit indicates which field is currently being displayed. The VDFLD bit is
updated at the start of the vertical blanking interval of the next field.
DEFAULT 0 Field 1 is active.
FIELD1ACT
FIELD2ACT 1 Field 2 is active.
11-0 VDXPOS OF( value) 0-FFFh Current frame pixel counter (FPCOUNT) value. Index of the most recently output
pixel.
DEFAULT 0
(1)
For CSL implementation, use the notation VD_VDSTAT_ field_ symval
For video display mode, field detect is enabled automatically when the VXS bit is set to 1 and the FXS bit
is cleared to 0. Ensure that the FXS bit is not set to 1 because this causes the video port to expect a filed
input on the pin.
SPRUEM1 – May 2007 Video Display Port 123
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