Video Port/VCXO Interpolated Control (VIC) Port User's Guide

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4.12.7 Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2)
Video Display Registers
Table 4-11. Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) Field Descriptions
Description
Bit field
(1)
symval
(1)
Value BT.656 and Y/C Mode Raw Data Mode
31-28 Reserved - 0 Reserved. The reserved bit location is always read as 0. A value written to this
field has no effect.
27-16 VBLNKYSTOP1 OF( value) 0-FFFh Specifies the line (in FLCOUNT) where Specifies the line (in FLCOUNT) where
VBLNK inactive edge occurs for field 1. vertical blanking ends (VBLNK inactive
Does not affect EAV/SAV V bit edge) for field 1.
operation.
DEFAULT 0
15-12 Reserved - 0 Reserved. The reserved bit location is always read as 0. A value written to this
field has no effect.
11-0 VBLNKXSTOP1 OF( value) 0-FFFh Specifies the pixel (in FPCOUNT) Specifies the pixel (in FPCOUNT)
where VBLNK inactive edge occurs for where vertical blanking ends (VBLNK
field 1. inactive edge) for field 1.
DEFAULT 0
(1)
For CSL implementation, use the notation VP_VDVBLKE1_ field_ symval
The video display field 2 vertical blanking start register (VDVBLKS2) controls the start of vertical blanking
in field 2.
In raw data mode, VBLNK is asserted whenever the frame line counter (FLCOUNT) is equal to
VBLNKYSTART2 and the frame pixel counter (FPCOUNT) is equal to VBLNKXSTART2 (this is shown in
Figure 4-6 .
In BT.656 and Y/C mode, VBLNK is asserted whenever FLCOUNT = VBLNKYSTART2 and FPCOUNT =
VBLNKXSTART2. This VBLNK output control is completely independent of the timing control codes. The
V bit in the EAV/SAV codes for field 2 is controlled by the VDVBIT2 register.
The video display field 2 vertical blanking start register (VDVBLKS2) is shown in Figure 4-37 and
described in Table 4-12 .
Figure 4-37. Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2)
31 28 27 16
Reserved VBLNKYSTART2
R-0 R/W-0
15 12 11 0
Reserved VBLNKXSTART2
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 4-12. Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) Field Descriptions
Description
Bit field
(1)
symval
(1)
Value BT.656 and Y/C Mode Raw Data Mode
31-28 Reserved - 0 Reserved. The reserved bit location is always read as 0. A value written to this
field has no effect.
27-16 VBLNKYSTART2 OF( value) 0-FFFh Specifies the line (in FLCOUNT) where Specifies the line (in FLCOUNT) where
VBLNK active edge occurs for field 2. vertical blanking begins (VBLNK active
Does not affect EAV/SAV V bit edge) for field 2.
operation.
DEFAULT 0
15-12 Reserved - 0 Reserved. The reserved bit location is always read as 0. A value written to this
field has no effect.
(1)
For CSL implementation, use the notation VP_VDVBLKS2_ field_ symval
130 Video Display Port SPRUEM1 – May 2007
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