Video Port/VCXO Interpolated Control (VIC) Port User's Guide

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4.12.16 Video Display Horizontal Synchronization Register (VDHSYNC)
4.12.17 Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1)
Video Display Registers
Table 4-20. Video Display Threshold Register (VDTHRLD) Field Descriptions (continued)
Description
Bit field
(1)
symval
(1)
Value BT.656 and Y/C Mode Raw Data Mode
11-10 Reserved - 0 Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
9-0 VDTHRLD1 OF( value) 0-3FFh Field 1 threshold. Whenever there are at Field 1 threshold. Whenever there are at
least VDTHRLD double words of space least VDTHRLD double words of space
in the Y display FIFO, a new Y EDMA in the display FIFO, a new Y EDMA
event may be generated. Whenever event may be generated.
there are at least ½ VDTHRLD double
words of space in the Cb or Cr display
FIFO, a new Cb or Cr EDMA event may
be generated.
DEFAULT 0
The video display horizontal synchronization register (VDHSYNC) controls the timing of the horizontal
synchronization signal.
Generation of the horizontal synchronization is shown in Figure 4-5 . The HSYNC signal is asserted to
indicate the start of the horizontal sync pulse whenever the frame pixel counter (FPCOUNT) is equal to
HSYNCSTART. The HSYNC signal is de-asserted to indicate the end of the horizontal sync pulse
whenever FPCOUNT = HSYNCSTOP.
Figure 4-46. Video Display Horizontal Synchronization Register (VDHSYNC)
31 28 27 16
Reserved HSYNCSTOP
R-0 R/W-0
15 12 11 0
Reserved HSYNCSTART
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 4-21. Video Display Horizontal Synchronization Register (VDHSYNC) Field Descriptions
Bit field
(1)
symval
(1)
Value Description
31-28 Reserved - 0 Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
27-16 HSYNCSTOP OF( value) 0-FFFh Specifies the pixel where HSYNC is de-asserted.
DEFAULT 0
15-12 Reserved - 0 Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
11-0 HSYNCSTART OF( value) 0-FFFh Specifies the pixel where HSYNC is asserted.
DEFAULT 0
(1)
For CSL implementation, use the notation VP_VDHSYNC_ field_ symval
The video display field 1 vertical synchronization start register (VDVSYNS1) controls the start of vertical
synchronization in field 1.
Generation of the vertical synchronization is shown in Figure 4-6 . The VSYNC signal is asserted
whenever the frame line counter (FLCOUNT) is equal to VSYNCYSTART1 and the frame pixel counter
(FPCOUNT) is equal to VSYNCXSTART1.
138 Video Display Port SPRUEM1 – May 2007
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