Video Port/VCXO Interpolated Control (VIC) Port User's Guide

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4.12.19 Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2)
4.12.20 Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2)
Video Display Registers
Table 4-23. Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1) Field Descriptions
(continued)
Bit field
(1)
symval
(1)
Value Description
15-12 Reserved - 0 Reserved. The reserved bit location is always read as 0. A value written to this
field has no effect.
11-0 VSYNCXSTOP1 OF( value) 0-FFFh Specifies the pixel where VSYNC is de-asserted in field 1.
DEFAULT 0
The video display field 2 vertical synchronization start register (VDVSYNS2) controls the start of vertical
synchronization in field 2. The VDVSYNS2 is shown in Figure 4-49 and described in Table 4-24 .
Generation of the vertical synchronization is shown in Figure 4-6 . The VSYNC signal is asserted
whenever the frame line counter (FLCOUNT) is equal to VSYNCYSTART2 and the frame pixel counter
(FPCOUNT) is equal to VSYNCXSTART2.
Figure 4-49. Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2)
31 28 27 16
Reserved VSYNCYSTART2
R-0 R/W-0
15 12 11 0
Reserved VSYNCXSTART2
R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; - n = value after reset
Table 4-24. Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2) Field
Descriptions
Bit field
(1)
symval
(1)
Value Description
31-28 Reserved - 0 Reserved. The reserved bit location is always read as 0. A value written to this
field has no effect.
27-16 VSYNCYSTART2 OF( value) 0-FFFh Specifies the line where VSYNC is asserted for field 2.
DEFAULT 0
15-12 Reserved - 0 Reserved. The reserved bit location is always read as 0. A value written to this
field has no effect.
11-0 VSYNCXSTART2 OF( value) 0-FFFh Specifies the pixel where VSYNC is asserted in field 2.
DEFAULT 0
(1)
For CSL implementation, use the notation VP_VDVSYNS2_ field_ symval
The video display field 2 vertical synchronization end register (VDVSYNE2) controls the end of vertical
synchronization in field 2. The VDVSYNE2 is shown in Figure 4-50 and described in Table 4-25 .
Generation of the vertical synchronization is shown in Figure 4-6 . The VSYNC signal is de-asserted
whenever the frame line counter (FLCOUNT) is equal to VSYNCYSTOP2 and the frame pixel counter
(FPCOUNT) is equal to VSYNCXSTOP2.
The video display field 2 vertical synchronization end register (VDVSYNE2) is shown in Figure 4-50 and
described in Table 4-25 .
Video Display Port140 SPRUEM1 – May 2007
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