Video Port/VCXO Interpolated Control (VIC) Port User's Guide

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Internal peripheral bus
Memory
mapped
registers
Raw video
display pipeline
Channel B
Channel A
Raw video
display pipeline
Y/C video
display pipeline
BT.656 display
pipeline
Y/C video
capture pipeline
Capture/display
buffer
(2560 bytes)
Raw video
capture pipeline
BT.656 capture
pipeline
TSI capture
pipeline
Raw video
capture pipeline
VDIN[19−12]
8
VDIN[19−2]
16
DMA interface
64
Capture/display
buffer
(2560 bytes)
8
8
8
16
16
8
16
16
Timing and
control logic
VCTL2
VCTL3
VCLK1
VCTL1
VCLK2
DMA interface
8 8
64
32
VDOUT[19−12]
8
VDOUT[19−2]
16
BT.656 capture
pipeline
Video Port
This document describes the full feature set offered by the video port. See the device-specific datasheet
for details about I/O timing information.
Figure 1-1. Video Port Block Diagram
Overview 18 SPRUEM1 – May 2007
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