Video Port/VCXO Interpolated Control (VIC) Port User's Guide

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Data Buffer
(5120 bytes)
VDIN[19−2]
16
Capture FIFO
YSRCA
64
1.2.3 Video Display FIFO Configurations
Y Buffer
(2560 bytes)
Cb Buffer
(1280 bytes)
Cr Buffer
(1280 bytes)
YDSTA
CBDST
CRDST
VDOUT[9−2]
Display FIFO
8
8
8
64
64
64
Data Buffer
(5120 bytes)
YDSTA
VDOUT[9−2]
64
8
Display FIFO
Video Port FIFO
For 16-bit raw video, the FIFO is configured as a single buffer, as shown in Figure 1-5 . The FIFO receives
16-bit data from the VDIN[19-2] bus. The FIFO has a single write pointer and read register (YSRCA).
Figure 1-5. 16-Bit Raw Video Capture FIFO Configuration
During video display operation, the video port FIFO has one of five configurations depending on the
display mode. For BT.656 operation, a single output is provided on channel A, as shown in Figure 1-6 ,
with data output on VDOUT[9-2]. The channel's FIFO is split into Y, Cb, and Cr buffers with separate read
pointers and write registers (YDSTA, CBDST, and CRDST).
Figure 1-6. BT.656 Video Display FIFO Configuration
For 8-bit raw video, the FIFO is configured as a single buffer as shown in Figure 1-7 . The FIFO outputs
data on the VDOUT[9-2] half of the bus. The FIFO has a single read pointer and write register (YDSTA).
Figure 1-7. 8-Bit Raw Video Display FIFO Configuration
SPRUEM1 – May 2007 Overview 23
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