Video Port/VCXO Interpolated Control (VIC) Port User's Guide

www.ti.com
2.1 Reset Operation
2.1.1 Power-On Reset
2.1.2 Peripheral Bus Reset
2.1.3 Software Port Reset
Reset Operation
The video port has several sources and types of resets. The actions performed by these resets and the
state of the port following the resets is described in the following sections.
Power-on reset is an asynchronous hardware reset caused by a chip-level reset operation. The reset is
initiated by a power-on reset input to the video port. When the input is active, the port places all I/Os
(VD[19-2], VCTL1, VCTL2, VCTL3, and VCLK1) in a high-impedance state.
Peripheral bus reset is a synchronous hardware reset caused by a chip-level reset operation. The reset is
initiated by a peripheral bus reset input to the video port. This reset can be used internally (continuously
asserted) to disable the video port for low-power operation. When the input is active, the port does the
following:
• Places (keeps) all I/Os (VD[19-2], VCTL1, VCTL2, VCTL3, and VCLK1) in a high-impedance state.
• Flushes the FIFOs (resets pointers)
• Resets all port, capture, display, and GPIO registers to their default values. These may not complete
until the appropriate module clock (VCLK1, STCLK) edges occur to synchronously release the logic
from reset.
• Clears PEREN bit in PCR to 0.
• Sets VPHLT bit in VPCTL to 1.
While the peripheral remains disabled (PEREN = 0):
• VCLK1, VCLK2, and STCLK are gated off to save peripheral power.
• Peripheral bus accesses are acknowledged (RREADY/WREADY returned) to prevent EDMA lock-up.
(Any value returned on reads, data accepted or discarded on writes.)
• Peripheral bus MMR interface allows access to GPIO registers only (PID, PCR, PFUNC, PDIR, PIN,
PDOUT, PDSET, PDCLR, PIEN, PIPOL, PISTAT, and PICLR).
• Port I/Os (VD[19-2], VCTL1, VCTL2, VCTL3, and VCLK2) remain in a high-impedance state unless
enabled as GPIO by the PFUNC bits.
If software sets the PEREN bit in PCR but the VPHLT bit in VPCTL remains set:
• VCLK1, VCLK2, and STCLK are enabled to the port (allowing logic reset to complete).
• Peripheral bus accesses are acknowledged (RREADY/WREADY returned) to prevent EDMA lock-up.
(Any value returned on reads, data accepted or discarded on writes.)
• Peripheral bus MMR interface allows access to all registers.
• Port I/Os (VD[19-2], VCTL1, VCTL2, VCTL3, and VCLK2) remain in a high-impedance state unless
enabled as GPIO by the PFUNC bits.
• VPCTL bits may be set (until the VPHLT bit is cleared).
A software port reset may be performed on the entire video port by setting the VPRST bit in VPCTL. This
behaves identically to the peripheral bus reset except that it does not clear the PEREN bit in PCR. This
reset:
• Performs a reset on all port logic (channel logic may stay in reset until port input clock pulses occur).
• Self-clears the VPRST bit to 0 but leaves the VPHLT bit set. The VCLK1 input must be clocking in
order for this reset to take effect.
30 Video Port SPRUEM1 – May 2007
Submit Documentation Feedback