Video Port/VCXO Interpolated Control (VIC) Port User's Guide

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3.8.6 Writing to the FIFO
TSI FIFO
            
VDIN[9−2]
VCLKIN
63 5655 4847 4039 32
TSI 5 TSI 4TSI 7 TSI 6
TSI 13 TSI 12TSI 15 TSI 14
Little-Endian Packing
       
31 2423 1615 87 0
TSI 1 TSI 0TSI 3 TSI 2
TSI 9 TSI 8TSI 11 TSI 10
3.8.7 Reading from the FIFO
TCI Capture Mode
Table 3-12. TCI Capture Mode Operation (continued)
VCACTL Bit
CON FRAME CF2 CF1 Operation
0 1 x x Single packet capture. FRMC is set after packet capture and causes CCMPA
to be set. Capture is halted until the FRMC bit is cleared.
1 0 x x Continuous packet capture. FRMC is set after packet capture and causes
CCMPA to be set (CCMPx interrupt can be disabled). The port will continue
capturing packets regardless of the state of FRMC.
1 1 x x Reserved
The captured TCI packet data and the associated time stamps are written into the receive FIFO. The
packet data is written first, followed by the timestamp. The FIFO controller controls both data writes and
timestamp writes into the FIFO. The FIFO data packing is shown in Figure 3-18 .
Figure 3-18. TCI FIFO Packing
The data capture circuitry signals to the synchronizing circuit when to take a timestamp of the hardware
counters. The FIFO write controller keeps track of the number of bytes received in a packet. It multiplexes
the timestamp data and the packet data onto the FIFO write data bus. The timestamp and packet error
information are inserted after each packet in the FIFO .The format for the timestamp is shown in
Figure 3-19 .
Figure 3-19. TCI Timestamp Format (Little Endian)
63 62 61 42 41 33 32
PERR PSTERR Reserved PCR extension PCR
31 0
PCR
The YSRCA location is associated with the TCI capture buffer. The YSRCA location is a read-only
pseudo-register and is used to access the TCI data samples stored in the buffer.
The captured data packet size is set by VCASTOP. The VCXSTOP and VCYSTOP bits set the 24-bits of
TCI packet size (VCXSTOP sets the lower 12 bits and VCYSTOP sets the upper 12 bits). Capture is
complete and the FRMC bit is set when the data counter equals the combined VCYSTOP and VCXSTOP
value.
66 Video Capture Port SPRUEM1 – May 2007
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