Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 80 (12x12) 32-Bit 60 MHz I/O number 45

TMS320F28030, TMS320F28031, TMS320F28032

TMS320F28033, TMS320F28034, TMS320F28035

www.ti.com

SPRS584J –APRIL 2009–REVISED OCTOBER 2013

Piccolo™ Microcontrollers

Check for Samples: TMS320F28030, TMS320F28031, TMS320F28032, TMS320F28033, TMS320F28034, TMS320F28035

1 TMS320F2803x (Piccolo) MCUs

1.1 Features

1234

• High-Efficiency 32-Bit CPU ( TMS320C28x™) • Peripheral Interrupt Expansion (PIE) Block That

Supports All Peripheral Interrupts

– 60 MHz (16.67-ns Cycle Time)

• Three 32-Bit CPU Timers

– 16 x 16 and 32 x 32 MAC Operations

• Independent 16-Bit Timer in Each ePWM

– 16 x 16 Dual MAC

Module

– Harvard Bus Architecture

• On-Chip Memory

– Atomic Operations

– Flash, SARAM, OTP, Boot ROM Available

– Fast Interrupt Response and Processing

• Code-Security Module

– Unified Memory Programming Model

• 128-Bit Security Key/Lock

– Code-Efficient (in C/C++ and Assembly)

– Protects Secure Memory Blocks

• Programmable Control Law Accelerator (CLA)

– Prevents Firmware Reverse Engineering

– 32-Bit Floating-Point Math Accelerator

• Serial Port Peripherals

– Executes Code Independently of the Main

– One SCI (UART) Module

CPU

– Two SPI Modules

• Endianness: Little Endian

– One Inter-Integrated-Circuit (I

C) Bus

• JTAG Boundary Scan Support

(1)

– One Local Interconnect Network (LIN) Bus

• Low Cost for Both Device and System:

– One Enhanced Controller Area Network

– Single 3.3-V Supply

(eCAN) Bus

– No Power Sequencing Requirement

• Enhanced Control Peripherals

– Integrated Power-on Reset and Brown-out

– Enhanced Pulse Width Modulator (ePWM)

Reset

– High-Resolution PWM (HRPWM) Module

– Low Power

– Enhanced Capture (eCAP) Module

– No Analog Support Pins

– High-Resolution Input Capture (HRCAP)

• Clocking:

Module

– Two Internal Zero-pin Oscillators

– Enhanced Quadrature Encoder Pulse (eQEP)

– On-Chip Crystal Oscillator/External Clock

Module

Input

– Analog-to-Digital Converter (ADC)

– Dynamic PLL Ratio Changes Supported

– On-Chip Temperature Sensor

– Watchdog Timer Module

– Comparator

– Missing Clock Detection Circuitry

• Advanced Emulation Features

• Up to 45 Individually Programmable,

– Analysis and Breakpoint Functions

Multiplexed GPIO Pins With Input Filtering

– Real-Time Debug via Hardware

• 2803x Packages

– 56-Pin RSH Very Small Quad Flatpack

(No Lead) (VQFN)

– 64-Pin PAG Thin Quad Flatpack (TQFP)

– 80-Pin PN Low-Profile Quad Flatpack (LQFP)

(1) IEEE Standard 1149.1-1990 Standard Test Access Port and

Boundary Scan Architecture

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Piccolo, TMS320C28x, C28x, TMS320C2000, Code Composer Studio, XDS510, XDS560 are trademarks of Texas

Instruments.

C-bus is a registered trademark of NXP B.V. Corporation.

4All other trademarks are the property of their respective owners.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information

current as of publication date. Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not necessarily include

testing of all parameters.

Summary of content (157 pages)

PAGE 1
TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Piccolo™ Microcontrollers Check for Samples: TMS320F28030, TMS320F28031, TMS320F28032, TMS320F28033, TMS320F28034, TMS320F28035 1 TMS320F2803x (Piccolo) MCUs 1.1 Features 1234 • High-Efficiency 32-Bit CPU ( TMS320C28x™) – 60 MHz (16.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 1.2 • • • • • • • • www.ti.com Applications Smart Grid and Power Line Communications White Goods Switch Mode Power Supplies (SMPSs) DC-DC Multiple-Output Power Supplies Solar Micro Inverters and Converters Power Factor Correction Sewing and Textile Machines AC-DC Inverters 1.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com 1.4 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Functional Block Diagram Figure 1-1 shows the functional block diagram for the device.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com ...................... 1 ............................................. 1 1.2 Applications .......................................... 2 1.3 Description ........................................... 2 1.4 Functional Block Diagram ........................... 3 1.5 Getting Started ....................................... 3 Revision History .....................................
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. This data manual revision history highlights the technical changes made to the SPRS584I device-specific data manual to make it an SPRS584J revision. Scope: See table below. LOCATION Section 1 Section 1.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 LOCATION 6 www.ti.com ADDITIONS, DELETIONS, AND MODIFICATIONS Section 4.5 Local Interconnect Network (LIN): • Added reference to TMS320F2803x Piccolo Local Interconnect Network (LIN) Module User's Guide (literature number SPRUGE2) Section 4.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 2 Introduction Table 2-1 lists the features of the TMS320F2803x devices.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com Table 2-1.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Table 2-1.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 2.1 www.ti.com Pin Assignments Figure 2-1 shows the 56-pin RSH Very Small Quad Flatpack (No Lead) (VQFN) pin assignments. Figure 2-2 shows the 64-pin PAG Thin Quad Flatpack (TQFP) pin assignments. Figure 2-3 shows the 80pin PN Low-Profile Quad Flatpack (LQFP) pin assignments. NOTE Information/data on the 56-pin RSH package is "TMX".
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GPIO35/TDI GPIO37/TDO GPIO38/TCK/XCLKIN GPIO19/XCLKIN/SPISTEA/LINRXA/ECAP1 VDD VSS X1 X2 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO GPIO7/EPWM4B/SCIRXDA GPIO12/TZ1/SCITXDA GPIO16/SPISIMOA/TZ2 GPIO17/SPISOMIA/TZ3 GPIO18/SPICLKA/LINTXA/XCLKOUT www.ti.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 GPIO28/SCIRXDA/SDAA/TZ2 GPIO9/EPWM5B/LINTXA/HRCAP1 TEST2 VDDIO VSS GPIO29/SCITXDA/SCLA/TZ3 GPIO30/CANRXA GPIO31/CANTXA ADCINB7 ADCINB6/COMP3B/AIO14 ADCINB4/COMP2B/AIO12 ADCINB3 ADCINB2/COMP1B/AIO10 ADCINB1 ADCINB0 VSSA/VREFLO A. B.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 GPIO8/EPWM5A/ADCSOCAO GPIO17/SPISOMIA/TZ3 GPIO18/SPICLKA/LINTXA/XCLKOUT 43 42 41 GPIO44 GPIO25/SPISOMIB 46 44 GPIO16/SPISIMOA/TZ2 47 45 GPIO41/EPWM7B GPIO12/TZ1/SCITXDA/SPISIMOB 48 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO GPIO7/EPWM4B/SCIRXDA 50 49 X1 X2 VSS 51 VDD 54 53 52 GPIO39 GPIO19/XCLKIN/SPISTEA/LINRXA/ECAP1 56 57 55 GPIO37/TDO GPIO38/TCK/XCLKIN 58 GPIO36/TMS GPIO35/TDI 60 SPRS584J – APRIL
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 2.2 www.ti.com Signal Descriptions Table 2-2 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. See Table 2-1 for details. Inputs are not 5-V tolerant.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Table 2-2. Terminal Functions(1) (continued) TERMINAL NAME PN PIN # PAG PIN # RSH PIN # I/O/Z DESCRIPTION O/Z See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com Table 2-2. Terminal Functions(1) (continued) TERMINAL NAME PN PIN # PAG PIN # RSH PIN # I/O/Z 17 14 12 I ADC Group A, Channel 1 input I ADC Group A, Channel 0 input. NOTE: VREFHI and ADCINA0 share the same pin on the 64-pin PAG device and their use is mutually exclusive to one another.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Table 2-2.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com Table 2-2.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Table 2-2. Terminal Functions(1) (continued) TERMINAL NAME GPIO18 PN PIN # PAG PIN # RSH PIN # I/O/Z 41 33 29 I/O/Z SPICLKA LINTXA XCLKOUT GPIO19 55 44 39 DESCRIPTION General-purpose input/output 18 I/O SPI-A clock input/output O LIN transmit O/Z Output clock derived from SYSCLKOUT.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com Table 2-2.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Table 2-2. Terminal Functions(1) (continued) TERMINAL NAME GPIO37 PN PIN # PAG PIN # RSH PIN # I/O/Z 58 46 41 I/O/Z General-Purpose Input/Output 37 O/Z JTAG scan out, test data output (TDO).
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com 3 Functional Overview 3.1 Memory Maps In Figure 3-1 through Figure 3-4, the following apply: • Memory blocks are not to scale. • Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps are restricted to data memory only. A user program cannot access these memory maps in program space.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Table 3-1.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com NOTE • When the code-security passwords are programmed, all addresses between 0x3F 7F80 and 0x3F 7FF5 cannot be used as program code or data. These locations must be programmed to 0x0000. • If the code security feature is not used, addresses 0x3F 7F80 through 0x3F 7FEF may be used for code or data.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com 3.2 3.2.1 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Brief Descriptions CPU The 2803x (C28x) family is a member of the TMS320C2000™ microcontroller (MCU) platform. The C28xbased controllers have the same 32-bit fixed-point architecture as existing C28x MCUs.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 3.2.4 www.ti.com Peripheral Bus To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the devices adopt a peripheral bus standard for peripheral interconnect.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com 3.2.8 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 L0 SARAM, and L1, L2, and L3 DPSARAMs The device contains up to 8K x 16 of single-access RAM. To ascertain the exact size for a given device, see the device-specific memory map figures in Section 3.1. This block is mapped to both program and data space. Block L0 is 2K in size and is dual mapped to both program and data space.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 3.2.9.3 www.ti.com Peripheral Pins Used by the Bootloader Table 3-7 shows which GPIO pins are used by each peripheral bootloader. Refer to the GPIO mux table to see if these conflict with any of the peripherals you would like to use in your application. Table 3-7.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 The solution is to use the Wait boot option. This will sit in a loop around a software breakpoint to allow an emulator to be connected without tripping security. Piccolo devices do not support a hardware wait-inreset mode. NOTE • When the code-security passwords are programmed, all addresses between 0x3F7F80 and 0x3F7FF5 cannot be used as program code or data.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com 3.2.12 External Interrupts (XINT1–XINT3) The devices support three masked external interrupts (XINT1–XINT3). Each of the interrupts can be selected for negative, positive, or both negative and positive edge triggering and can also be enabled/disabled.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 3.2.17 Peripheral Frames 0, 1, 2, 3 (PFn) The device segregates peripherals into four sections.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com 3.2.19 32-Bit CPU-Timers (0, 1, 2) CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The timers have a 32-bit count-down register, which generates an interrupt when the counter reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 3.2.21 Serial Port Peripherals The devices support the following serial communication peripherals: SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 3.3 www.ti.com Register Map The devices contain four peripheral register spaces. The spaces are categorized as follows: Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus. See Table 3-8. Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See Table 3-9.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Table 3-10.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 3.4 www.ti.com Device Emulation Registers These registers are used to control the protection mode of the C28x CPU and to monitor some critical device signals. The registers are defined in Table 3-12 . Table 3-12.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com 3.5 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Interrupts Figure 3-5 shows how the various interrupt sources are multiplexed.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts per group equals 96 possible interrupts. Table 3-13 shows the interrupts used by 2803x devices. The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to the vector specified.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Table 3-13. PIE MUXed Peripheral Interrupt Vector Table (1) INT1.y INT2.y INT3.y INT4.y INT5.y INT6.y INT7.y INT8.y INT9.y INT10.y INT11.y INT12.y (1) INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 WAKEINT TINT0 ADCINT9 XINT2 XINT1 Reserved ADCINT2 ADCINT1 (LPM/WD) (TIMER 0) (ADC) Ext. int. 2 Ext. int.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com Table 3-14.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com 3.5.1 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 External Interrupts Table 3-15.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 3.6.2 www.ti.com On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit Two on-chip supervisory circuits, the power-on reset (POR) and the brown-out reset (BOR) remove the burden of monitoring the VDD and VDDIO supply rails from the application board. The purpose of the POR is to create a clean reset throughout the device during the entire power-up procedure.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com 3.7 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 System Control This section describes the oscillator and clocking mechanisms, the watchdog function and the low power modes. Table 3-16.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com Figure 3-8 shows the various clock domains that are discussed. Figure 3-9 shows the various clock sources (both internal and external) that can provide a clock for device operation.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 3.7.1 www.ti.com Internal Zero Pin Oscillators The F2803x devices contain two independent internal zero pin oscillators. By default both oscillators are turned on at power up, and internal oscillator 1 is the default clock source at this time. For power savings, unused oscillators may be powered down by the user.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com 3.7.3 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 PLL-Based Clock Module The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com The PLL-based clock module provides four modes of operation: • INTOSC1 (Internal Zero-pin Oscillator 1): This is the on-chip internal oscillator 1. This can provide the clock for the Watchdog block, core and CPU-Timer 2 • INTOSC2 (Internal Zero-pin Oscillator 2): This is the on-chip internal oscillator 2.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 NMIFLG[NMINT] NMIFLGCLR[NMINT] Clear Latch Set Clear XRS NMINT Generate Interrupt Pulse When Input = 1 1 0 NMIFLG[CLOCKFAIL] Clear Latch Clear Set 0 NMIFLGCLR[CLOCKFAIL] CLOCKFAIL SYNC? SYSCLKOUT NMICFG[CLOCKFAIL] XRS NMIFLGFRC[CLOCKFAIL] SYSCLKOUT SYSRS NMIWDPRD[15:0] NMIWDCNT[15:0] NMI Watchdog NMIRS See System Control Section Figure 3-12.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com WDCR (WDPS[2:0]) WDCR (WDDIS) WDCNTR(7:0) WDCLK Watchdog Prescaler /512 WDCLK 8-Bit Watchdog Counter CLR Clear Counter Internal Pullup WDKEY(7:0) Watchdog 55 + AA Key Detector WDRST Generate Output Pulse WDINT (512 OSCCLKs) Good Key XRS Core-reset WDCR (WDCHK[2:0]) WDRST(A) A.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com 3.8 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Low-power Modes Block Table 3-21 summarizes the various modes. Table 3-21.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com 4 Peripherals 4.1 Control Law Accelerator (CLA) Overview The control law accelerator extends the capabilities of the C28x CPU by adding parallel processing. Timecritical control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA enables faster system response and higher frequency control loops.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com Table 4-1.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com 4.2 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Analog Block A 12-bit ADC core is implemented that has different timings than the 12-bit ADC used on F280x/F2833x. The ADC wrapper is modified to incorporate the new timings and also other enhancements to improve the timing control of start of conversions. Figure 4-2 shows the interaction of the analog module with the rest of the F2803x system.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 4.2.1 www.ti.com ADC 4.2.1.1 Features The core of the ADC contains a single 12-bit converter fed by two sample-and-hold circuits. The sampleand-hold circuits can be sampled simultaneously or sequentially. These, in turn, are fed by a total of up to 16 analog input channels.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Table 4-3.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com 4.2.2 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 ADC MUX To COMPy A or B input To ADC Channel X Logic implemented in GPIO MUX block AIOx Pin SYSCLK AIOxIN 1 AIOxINE AIODAT Reg (Read) SYNC 0 AIODAT Reg (Latch) AIOxDIR (1 = Input, 0 = Output) AIOMUX 1 Reg AIOSET, AIOCLEAR, AIOTOGGLE Regs AIODIR Reg (Latch) 1 (0 = Input, 1 = Output) 0 0 Figure 4-4.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 4.2.3 www.ti.com Comparator Block Figure 4-5 shows the interaction of the Comparator modules with the rest of the system. COMP x A COMP x B + COMP - GPIO MUX COMP x + DAC x Wrapper AIO MUX TZ1/2/3 ePWM COMPxOUT DAC Core 10-Bit Figure 4-5. Comparator Block Diagram Table 4-5.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com 4.3 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Serial Peripheral Interface (SPI) Module The device includes the four-pin serial peripheral interface (SPI) module. Up to two SPI modules are available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bittransfer rate.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com The SPI port operation is configured and controlled by the registers listed in Table 4-6 and Table 4-7. Table 4-6.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Figure 4-6 is a block diagram of the SPI in slave mode. SPIFFENA SPIFFTX.14 Receiver Overrun Flag RX FIFO Registers SPISTS.7 Overrun INT ENA SPICTL.4 SPIRXBUF RX FIFO _0 RX FIFO _1 ----- SPIINT RX FIFO Interrupt RX FIFO _3 RX Interrupt Logic 16 SPIRXBUF Buffer Register SPIFFOVF FLAG SPIFFRX.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 4.4 www.ti.com Serial Communications Interface (SCI) Module The devices include one serial communications interface (SCI) module (SCI-A). The SCI module supports digital communications between the CPU and other asynchronous peripherals that use the standard nonreturn-to-zero (NRZ) format.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 The SCI port operation is configured and controlled by the registers listed in Table 4-8. Table 4-8.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com For more information on the SCI, see the TMS320x2802x, 2803x Piccolo Serial Communications Interface (SCI) Reference Guide (literature number SPRUGH1). Figure 4-7 shows the SCI module block diagram. SCICTL1.1 SCITXD Frame Format and Mode Parity Even/Odd Enable TXSHF Register TXENA 8 SCICCR.6 SCICCR.5 TX EMPTY SCICTL2.6 TXRDY TXWAKE SCICTL1.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com 4.5 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Local Interconnect Network (LIN) The device contains one LIN controller. The LIN standard is based on the SCI (UART) serial data link format. The LIN module can be configured to work as a SCI as well. The LIN module has the following features: • Compatible to LIN 1.3 or 2.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com The registers in Table 4-9 configure and control the operation of the LIN module. Table 4-9.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Figure 4-8 shows the LIN module block diagram. READ DATA BUS WRITE DATA BUS ADDRESS BUS CHECKSUM CALCULATOR INTERFACE ID PARTY CHECKER BIT MONITOR TXRX ERROR DETECTOR (TED) TIMEOUT CONTROL COUNTER LINRX/ SCIRX COMPARE LINTX/ SCITX FSM MASK FILTER SYNCHRONIZER 8 RECEIVE BUFFERS 8 TRANSMIT BUFFERS Figure 4-8.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 4.6 www.ti.com Enhanced Controller Area Network (eCAN) Module The CAN module (eCAN-A) has the following features: • Fully compliant with CAN protocol, version 2.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 The CAN registers listed in Table 4-11 are used by the CPU to configure and control the CAN controller and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary. Table 4-11.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 4.7 www.ti.com Inter-Integrated Circuit (I2C) The device contains one I2C Serial Port. Figure 4-11 shows how the I2C peripheral module interfaces within the device. The I2C module has the following features: • Compliance with the Philips Semiconductors I2C-bus specification (version 2.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 2 I C Module I2CXSR I2CDXR TX FIFO FIFO Interrupt to CPU/PIE SDA RX FIFO Peripheral Bus I2CRSR SCL I2CDRR Clock Synchronizer Control/Status Registers CPU Prescaler Noise Filters Interrupt to CPU/PIE I2C INT Arbitrator A. B. The I2C registers are accessed at the SYSCLKOUT rate.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 4.8 www.ti.com Enhanced PWM Modules (ePWM1/2/3/4/5/6/7) The devices contain up to seven enhanced PWM Modules (ePWM). Figure 4-12 shows a block diagram of multiple ePWM modules. Figure 4-13 shows the signal interconnections with the ePWM. See the TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) Module Reference Guide (literature number SPRUGE9) for more details.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com Table 4-13.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Table 4-13.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com Table 4-14.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Table 4-14.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com 4.9 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 High-Resolution PWM (HRPWM) This module combines multiple delay lines in a single module and a simplified calibration system by using a dedicated calibration delay line. For each ePWM module there is one HR delay line.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com 4.10 Enhanced Capture Module (eCAP1) SYNC The device contains an enhanced capture (eCAP) module. Figure 4-14 shows a functional block diagram of a module.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Table 4-15.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com 4.11 High-Resolution Capture (HRCAP) Module The High-Resolution Capture (HRCAP) module measures the difference between external pulses with a typical resolution of 300 ps.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Table 4-16.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com 4.12 Enhanced Quadrature Encoder Pulse (eQEP) The device contains one enhanced quadrature encoder pulse (eQEP) module. Table 4-17.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Figure 4-16 shows the eQEP functional block diagram.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com 4.13 JTAG Port On the 2803x device, the JTAG port is reduced to 5 pins (TRST, TCK, TDI, TMS, TDO). TCK, TDI, TMS and TDO pins are also GPIO pins. The TRST signal selects either JTAG or GPIO operating mode for the pins in Figure 4-17. During emulation/debug, the GPIO function of these pins are not available.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 4.14 GPIO MUX The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to providing individual pin bit-banging I/O capability. The device supports 45 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations).
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com Table 4-19.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Table 4-20.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from four choices: • Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com 5 Device Support Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of MCUs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 5.2 www.ti.com Related Documentation Extensive documentation supports all of the TMS320™ MCU family generations of devices from product announcement through applications development. The types of documentation available include: data sheets and data manuals, with design specifications; and hardware and software applications.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 SPRUGO0 TMS320x2803x Piccolo Boot ROM Reference Guide describes the purpose and features of the boot loader (factory-programmed boot-loading software) and provides examples of code. It also describes other contents of the device on-chip boot ROM and identifies where all of the information is located within that memory.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 5.3 www.ti.com Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 6 Electrical Specifications 6.1 Absolute Maximum Ratings (1) (2) Supply voltage range, VDDIO (I/O and Flash) with respect to VSS –0.3 V to 4.6 V Supply voltage range, VDD with respect to VSS –0.3 V to 2.5 V Analog voltage range, VDDA with respect to VSSA –0.3 V to 4.6 V Input voltage range, VIN (3.3 V) –0.3 V to 4.6 V Output voltage range, VO –0.3 V to 4.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 6.3 www.ti.com Electrical Characteristics (1) over recommended operating conditions (unless otherwise noted) PARAMETER VOH High-level output voltage VOL Low-level output voltage IIL IIH Input current (low level) Input current (high level) TEST CONDITIONS MIN IOH = IOH MAX 2.4 IOH = 50 μA V VDDIO – 0.2 IOL = IOL MAX 0.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com 6.4 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Current Consumption Table 6-1.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 6.4.1 www.ti.com Reducing Current Consumption The 2803x devices incorporate a method to reduce the device current consumption. Since each peripheral unit has an individual clock-enable bit, significant reduction in current consumption can be achieved by turning off the clock to any peripheral module that is not used in a given application.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com 6.4.2 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Current Consumption Graphs (VREG Enabled) Operational Current vs Frequency 140 Operational Current (mA) 120 100 80 60 40 20 0 0 10 20 30 40 50 60 70 60 70 SYSCLKOUT (MHz) IDDIO IDDA Figure 6-1.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com Typical CLA operational current vs SYSCLKOUT CLA operational IDDIO current (mA) 25 20 15 10 5 0 10 15 20 25 30 35 40 45 50 55 60 SYSCLKOUT (MHz) Figure 6-3.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com 6.5 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Thermal Design Considerations Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems that exceed the recommended maximum power dissipation in the end product may require additional thermal enhancements. Ambient temperature (TA) varies with the end application and product design.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 6.7 www.ti.com Timing Parameter Symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: 6.7.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com 6.7.3 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Device Clock Table This section provides the timing requirements and switching characteristics for the various clock options available on the 2803x MCUs. Table 6-3 lists the cycle times of various clocks. Table 6-3.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com Table 6-5. Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics PARAMETER MIN TYP MAX UNIT Internal zero-pin oscillator 1 (INTOSC1) at 30°C (1) (2) Frequency 10.000 MHz Internal zero-pin oscillator 2 (INTOSC2) at 30°C (1) (2) Frequency 10.000 MHz 55 kHz Step size (coarse trim) Step size (fine trim) 14 Temperature drift (3) 3.03 4.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com 6.8 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Clock Requirements and Characteristics Table 6-6. XCLKIN Timing Requirements - PLL Enabled NO.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 6.9 www.ti.com Power Sequencing There is no power sequencing requirement needed to ensure the device is in the proper state after reset or to prevent the I/Os from glitching during power up/down (GPIO19, GPIO34–38 do not have glitch-free I/Os). No voltage larger than a diode drop (0.7 V) above VDDIO should be applied to any digital pin (for analog pins, it is 0.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Table 6-9. Reset (XRS) Timing Requirements MIN th(boot-mode) Hold time for boot-mode pins tw(RSL2) Pulse duration, XRS low on warm reset NOM MAX UNIT 1000tc(SCO) cycles 32tc(OSCCLK) cycles Table 6-10.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com Figure 6-10 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR = 0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com 6.10.2 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 GPIO - Input Timing Table 6-12.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com 6.10.3 Sampling Window Width for Input Signals The following section summarizes the sampling window width for input signals for various input qualifier configurations. Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 6.10.4 Low-Power Mode Wakeup Timing Table 6-13 shows the timing requirements, Table 6-14 shows the switching characteristics, and Figure 615 shows the timing diagram for IDLE mode. Table 6-13.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com Table 6-15. STANDBY Mode Timing Requirements tw(WAKE-INT) (1) Pulse duration, external wake-up signal TEST CONDITIONS MIN Without input qualification 3tc(OSCCLK) With input qualification (1) NOM MAX UNIT cycles (2 + QUALSTDBY) * tc(OSCCLK) QUALSTDBY is a 6-bit field in the LPMCR0 register. Table 6-16.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 (C) (A) (B) Device Status (F) (D)(E) STANDBY (G) STANDBY Normal Execution Flushing Pipeline Wake-up (H) Signal tw(WAKE-INT) td(WAKE-STBY) X1/X2 or XCLKIN XCLKOUT td(IDLE−XCOL) A. B. C. D. E. F. G. H. IDLE instruction is executed to put the device into STANDBY mode. The PLL block responds to the STANDBY signal.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com (C) (A) (F) (B) Device Status HALT Flushing Pipeline (H) (G) (D)(E) HALT PLL Lock-up Time Wake-up Latency Normal Execution (I) GPIOn td(WAKE−HALT ) tw(WAKE-GPIO) tp X1/X2 or XCLKIN Oscillator Start-up Time XCLKOUT td(IDLE−XCOL) A. B. C. D. E. F. G. H. I. IDLE instruction is executed to put the device into HALT mode.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 6.11 Enhanced Control Peripherals 6.11.1 Enhanced Pulse Width Modulator (ePWM) Timing PWM refers to PWM outputs on ePWM1–7. Table 6-19 shows the PWM timing requirements and Table 620, switching characteristics. Table 6-19.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com 6.11.3 High-Resolution PWM (HRPWM) Timing Table 6-22 shows the high-resolution PWM switching characteristics. Table 6-22. High-Resolution PWM Characteristics (1) MIN TYP MAX UNIT 150 310 ps Micro Edge Positioning (MEP) step size (2) (1) (2) The HRPWM operates at a minimum SYSCLKOUT frequency of 60 MHz.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 6.11.6 Enhanced Quadrature Encoder Pulse (eQEP) Timing Table 6-26 shows the eQEP timing requirement and Table 6-27 shows the eQEP switching characteristics. Table 6-26.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com 6.11.8 External Interrupt Timing Table 6-29. External Interrupt Timing Requirements (1) TEST CONDITIONS tw(INT) (1) (2) (2) Pulse duration, INT input low/high MIN MAX UNIT Synchronous 1tc(SCO) cycles With qualifier 1tc(SCO) + tw(IQSW) cycles For an explanation of the input qualifier parameters, see Table 6-12.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 6.11.9 I2C Electrical Specification and Timing Table 6-31.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com Table 6-32. SPI Master Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5) SPI WHEN (SPIBRR + 1) IS EVEN OR SPIBRR = 0 OR 2 NO. MIN SPI WHEN (SPIBRR + 1) IS ODD AND SPIBRR > 3 MAX MIN UNIT MAX 1 tc(SPC)M Cycle time, SPICLK 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) ns 2 tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 10 0.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 4 5 SPISIMO Master Out Data Is Valid 8 9 SPISOMI Master In Data Must Be Valid (A) SPISTE A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com Table 6-33. SPI Master Mode External Timing (Clock Phase = 1) (1) (2) (3) (4) (5) SPI WHEN (SPIBRR + 1) IS EVEN OR SPIBRR = 0 OR 2 NO. MIN MAX SPI WHEN (SPIBRR + 1) IS ODD AND SPIBRR > 3 MIN UNIT MAX 1 tc(SPC)M Cycle time, SPICLK 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) ns 2 tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 10 0.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 6 7 SPISIMO Master out data Is valid Data Valid 10 11 SPISOMI Master in data must be valid SPISTE(A) A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com 6.11.11 SPI Slave Mode Timing Table 6-34 lists the slave mode external timing (clock phase = 0) and Table 6-35 (clock phase = 1). Figure 6-23 and Figure 6-24 show the timing waveforms. Table 6-34. SPI Slave Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5) NO.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Table 6-35. SPI Slave Mode External Timing (Clock Phase = 1) (1) (2) (3) (4) NO. MIN MAX 12 tc(SPC)S Cycle time, SPICLK 13 tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 0.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com 6.11.12 On-Chip Comparator/DAC Table 6-36.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 6.11.13 On-Chip Analog-to-Digital Converter Table 6-37. ADC Electrical Characteristics PARAMETER MIN TYP MAX UNIT DC SPECIFICATIONS Resolution 12 Bits ADC clock 60-MHz device 0.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com Table 6-38.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 ADCIN Rs Source Signal Ron 3.4 kW Switch Cp 5 pF ac Ch 1.6 pF 28x DSP Typical Values of the Input Circuit Components: Switch Resistance (Ron): 3.4 k W Sampling Capacitor (Ch): 1.6 pF Parasitic Capacitance (Cp): 5 pF Source Resistance (Rs): 50 W Figure 6-27.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com 6.11.13.3 ADC Sequential and Simultaneous Timings Analog Input SOC0 Sample Window 0 2 SOC1 Sample Window 9 15 SOC2 Sample Window 22 24 37 ADCCLK ADCCTL 1.INTPULSEPOS ADCSOCFLG 1.SOC0 ADCSOCFLG 1.SOC1 ADCSOCFLG 1.SOC2 S/H Window Pulse to Core SOC0 ADCRESULT 0 SOC1 2 ADCCLKs SOC2 Result 0 Latched ADCRESULT 1 EOC0 Pulse EOC1 Pulse ADCINTFLG .
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Analog Input SOC0 Sample Window 0 2 SOC1 Sample Window 9 15 SOC2 Sample Window 22 24 37 ADCCLK ADCCTL1.INTPULSEPOS ADCSOCFLG 1.SOC0 ADCSOCFLG 1.SOC1 ADCSOCFLG 1.SOC2 S/H Window Pulse to Core SOC0 SOC1 SOC2 Result 0 Latched ADCRESULT 0 ADCRESULT 1 EOC0 Pulse EOC1 Pulse EOC2 Pulse ADCINTFLG .
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com Analog Input A SOC0 Sample A Window SOC2 Sample A Window SOC0 Sample B Window SOC2 Sample B Window Analog Input B 0 2 9 22 24 37 50 ADCCLK ADCCTL1.INTPULSEPOS ADCSOCFLG 1.SOC0 ADCSOCFLG 1.SOC1 ADCSOCFLG 1.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 Analog Input A SOC0 Sample A Window SOC2 Sample A Window SOC0 Sample B Window SOC2 Sample B Window Analog Input B 0 9 2 22 24 37 50 ADCCLK ADCCTL1.INTPULSEPOS ADCSOCFLG1.SOC0 ADCSOCFLG1.SOC1 ADCSOCFLG1.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com 6.12 Detailed Descriptions Integral Nonlinearity Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. The point used as zero occurs one-half LSB before the first code transition. The full-scale point is defined as level one-half LSB beyond the last code transition.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 6.13 Flash Timing Table 6-41.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 www.ti.com Table 6-46. Flash Data Retention Duration PARAMETER tretention TEST CONDITIONS Data retention duration TJ = 55°C MIN MAX 15 UNIT years Table 6-47. Minimum Required Flash/OTP Wait-States at Different Frequencies (1) SYSCLKOUT (MHz) SYSCLKOUT (ns) PAGE WAIT-STATE (1) RANDOM WAIT-STATE (1) OTP WAIT-STATE 60 16.67 2 2 3 55 18.
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TMS320F28030, TMS320F28031, TMS320F28032 TMS320F28033, TMS320F28034, TMS320F28035 www.ti.com SPRS584J – APRIL 2009 – REVISED OCTOBER 2013 7 Thermal/Mechanical Data Table 7-1, Table 7-2, and Table 7-3 show the thermal data. See Section 6.5 for more information on thermal design considerations. The mechanical package diagrams that follow the tables reflect the most current released mechanical data available for the designated devices. Table 7-1.
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MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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MECHANICAL DATA MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996 PN (S-PQFP-G80) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 41 60 61 40 80 21 0,13 NOM 1 20 Gage Plane 9,50 TYP 12,20 SQ 11,80 14,20 SQ 13,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040135 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 30-Aug-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
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