Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 (14x14) 32-Bit 90 MHz I/O number 54

TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066

TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

www.ti.com

SPRS698D –NOVEMBER 2010–REVISED DECEMBER 2012

Piccolo Microcontrollers

Check for Samples: TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066,

TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

1 TMS320F2806x ( Piccolo™) MCUs

1.1 Features

123

• High-Efficiency 32-Bit CPU (TMS320C28x™) • Clocking

– 90 MHz (11.11-ns Cycle Time) – Two Internal Zero-pin Oscillators

– 16 x 16 and 32 x 32 MAC Operations – On-Chip Crystal Oscillator/External Clock

Input

– 16 x 16 Dual MAC

– Dynamic PLL Ratio Changes Supported

– Harvard Bus Architecture

– Watchdog Timer Module

– Atomic Operations

– Missing Clock Detection Circuitry

– Fast Interrupt Response and Processing

• Peripheral Interrupt Expansion (PIE) Block That

– Unified Memory Programming Model

Supports All Peripheral Interrupts

– Code-Efficient (in C/C++ and Assembly)

• Three 32-Bit CPU Timers

• Floating-Point Unit

• Advanced Control Peripherals

– Native Single-Precision Floating-Point

• Up to 8 Enhanced Pulse Width Modulator

Operations

(ePWM) Modules

• Programmable Control Law Accelerator (CLA)

– 16 PWM Channels Total (8 HRPWM-Capable)

– 32-Bit Floating-Point Math Accelerator

– Independent 16-Bit Timer in Each Module

– Executes Code Independently of the Main

• Three Input Capture (eCAP) Modules

CPU

• Up to 4 High-Resolution Input Capture (HRCAP)

• Viterbi, Complex Math, CRC Unit (VCU)

Modules

– Extends C28x™ Instruction Set to Support

• Up to 2 Quadrature Encoder (eQEP) Modules

Complex Multiply, Viterbi Operations, and

Cyclic Redundency Check (CRC) • 12-Bit ADC, Dual Sample-and-Hold (S/H)

• Embedded Memory – Up to 3.46 MSPS

– Up to 256KB Flash – Up to 16 Channels

– Up to 100KB RAM • On-Chip Temperature Sensor

– 2KB OTP ROM • 128-Bit Security Key and Lock

• 6-Channel DMA – Protects Secure Memory Blocks

• Low Device and System Cost – Prevents Firmware Reverse Engineering

– Single 3.3-V Supply • Serial Port Peripherals

– No Power Sequencing Requirement – Two Serial Communications Interface (SCI)

[UART] Modules

– Integrated Power-on Reset and Brown-out

Reset – Two Serial Peripheral Interface (SPI)

Modules

– Low-Power Operating Modes

– One Inter-Integrated-Circuit (I2C) Bus

– No Analog Support Pin

– One Multichannel Buffered Serial Port

• Endianness: Little Endian

(McBSP) Bus

– One Enhanced Controller Area Network

(eCAN)

– One Universal Serial Bus (USB) 2.0 Module

(Available on TMS320F2806xU Devices Only)

• Full-Speed Device Mode

• Full-Speed or Low-Speed Host Mode

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Piccolo, PowerPAD, C28x, TMS320C2000, C2000, ControlSUITE, Code Composer Studio, XDS510, XDS560, TMS320C28x,

TMS320C54x, TMS320C55x are trademarks of Texas Instruments.

3All other trademarks are the property of their respective owners.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information

current as of publication date. Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not necessarily include

testing of all parameters.

Summary of content (173 pages)

PAGE 1
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Piccolo Microcontrollers Check for Samples: TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066, TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 1 TMS320F2806x ( Piccolo™) MCUs 1.1 Features 123 • High-Efficiency 32-Bit CPU (TMS320C28x™) – 90 MHz (11.
PAGE 2
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 • Up to 54 Individually Programmable, Multiplexed GPIO Pins With Input Filtering • Advanced Emulation Features – Analysis and Breakpoint Functions – Real-Time Debug via Hardware 1.2 www.ti.
PAGE 3
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 1.
PAGE 4
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 1.4 www.ti.
PAGE 5
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 1 2 3 .................. 1 ............................................. 1 1.2 Description ........................................... 2 1.3 Functional Block Diagram ........................... 3 1.4 System Device Diagram ............................. 4 Device Overview ........................................ 6 2.1 Device Characteristics ............................... 6 2.
PAGE 6
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com 2 Device Overview 2.1 Device Characteristics Table 2-1 lists the features of the TMS320F2806x devices.
PAGE 7
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Table 2-1. Hardware Features FEATURE Package Type (PFP and PZP are HTQFPs. PN and PZ are LQFPs.
PAGE 8
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com Table 2-1. Hardware Features (continued) FEATURE 28069, 28069U (2) (90 MHz) TYPE (1) Package Type (PFP and PZP are HTQFPs. PN and PZ are LQFPs.
PAGE 9
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 2.2 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Memory Maps In Figure 2-1 through Figure 2-7, the following apply: • Memory blocks are not to scale. • Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps are restricted to data memory only. A user program cannot access these memory maps in program space.
PAGE 10
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.
PAGE 11
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.
PAGE 12
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.
PAGE 13
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.
PAGE 14
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.
PAGE 15
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.
PAGE 16
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.
PAGE 17
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Table 2-2.
PAGE 18
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com Peripheral Frame 1 and Peripheral Frame 2 are grouped together to enable these blocks to be write/read peripheral block protected. The protected mode makes sure that all accesses to these blocks happen as written.
PAGE 19
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 2.
PAGE 20
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 GPIO8/EPWM5A/ADCSOCAO GPIO52/EQEP1S/MCLKXA/TZ3 GPIO17/SPISOMIA/TZ3 GPIO18/SPICLKA/SCITXDB/XCLKOUT 53 52 51 GPIO16/SPISIMOA/TZ2 55 54 GPIO7/EPWM4B/SCIRXDA/ECAP2 GPIO44/MFSRA/SCIRXDB/EPWM7B 56 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO 58 57 X1 X2 VDDIO 61 59 VSS 62 60 GPIO19/XCLKIN/SPISTEA/SCIRXDB/ECAP1 VDD 63 GPIO53/EQEP1I/MFSXA 65 64 GPIO38/XCLKIN/TCK GPIO39 66 GPIO34/COMP2OUT/COMP3
PAGE 21
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 2.4 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Signal Descriptions Table 2-5 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. See Table 2-1 for details.
PAGE 22
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com Table 2-5. Terminal Functions(1) (continued) PIN NO. PIN NAME PZ PZP PN PFP I/O/Z DESCRIPTION O/Z See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register.
PAGE 23
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Table 2-5. Terminal Functions(1) (continued) PIN NO. PIN NAME I/O/Z DESCRIPTION PZ PZP PN PFP VREFHI 24 19 ADCINB7 35 – I ADC Group B, Channel 7 input ADCINB6 34 27 I ADC Group B, Channel 6 input I Comparator Input 3B COMP3B AIO14 ADC External Reference – only used when in ADC external reference mode. See Section 5.
PAGE 24
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com Table 2-5. Terminal Functions(1) (continued) PIN NO. PIN NAME PZ PZP PN PFP I/O/Z 90 71 I DESCRIPTION VOLTAGE REGULATOR CONTROL SIGNAL VREGENZ Internal VREG Enable/Disable. Pull low to enable VREG, pull high to disable VREG.
PAGE 25
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Table 2-5. Terminal Functions(1) (continued) PIN NO.
PAGE 26
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com Table 2-5. Terminal Functions(1) (continued) PIN NO. PIN NAME GPIO18 PZ PZP PN PFP I/O/Z 51 41 I/O/Z SPICLKA DESCRIPTION General-purpose input/output 18 I/O SPI-A clock input/output SCITXDB O SCI-B transmit data XCLKOUT O/Z Output clock derived from SYSCLKOUT.
PAGE 27
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Table 2-5. Terminal Functions(1) (continued) PIN NO. PIN NAME GPIO26 PZ PZP PN PFP I/O/Z 78 62 DESCRIPTION I/O/Z General-purpose input/output 26 ECAP3 I/O Enhanced Capture input/output 3 EQEP2I I/O Enhanced QEP2 index. NOTE: eQEP2 is only available in the PZ and PZP packages.
PAGE 28
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com Table 2-5. Terminal Functions(1) (continued) PIN NO. PIN NAME GPIO35 PZ PZP PN PFP I/O/Z 71 57 I/O/Z TDI I GPIO36 72 58 TMS I/O/Z I GPIO37 70 56 TDO GPIO38 67 54 XCLKIN TCK DESCRIPTION General-purpose input/output 35 JTAG test data input (TDI) with internal pullup.
PAGE 29
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Table 2-5. Terminal Functions(1) (continued) PIN NO.
PAGE 30
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 2.5 2.5.1 www.ti.com Brief Descriptions CPU The 2806x (C28x) family is a member of the TMS320C2000™ microcontroller (MCU) platform. The C28xbased controllers have the same 32-bit fixed-point architecture as existing C28x MCUs.
PAGE 31
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 2.5.3 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Viterbi, Complex Math, CRC Unit (VCU) The C28x VCU enhances the processing power of C2000™ devices by adding additional assembly instructions to target complex math, Viterbi decode, and CRC calculations.
PAGE 32
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 2.5.5 www.ti.com Peripheral Bus To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the devices adopt a peripheral bus standard for peripheral interconnect.
PAGE 33
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 2.5.8 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 M0, M1 SARAMs All devices contain these two blocks of single-access memory, each 1K x 16 in size. The stack pointer points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x devices, are mapped to both program and data space.
PAGE 34
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com 2.5.10.3 Peripheral Pins Used by the Bootloader Table 2-7 shows which GPIO pins are used by each peripheral bootloader. Refer to the GPIO mux table to see if these conflict with any of the peripherals you would like to use in your application. Table 2-7.
PAGE 35
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 The solution is to use the Wait boot option. This will sit in a loop around a software breakpoint to allow an emulator to be connected without tripping security. Piccolo devices do not support a hardware wait-inreset mode.
PAGE 36
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com 2.5.13 External Interrupts (XINT1–XINT3) The devices support three masked external interrupts (XINT1–XINT3). Each of the interrupts can be selected for negative, positive, or both negative and positive edge triggering and can also be enabled or disabled.
PAGE 37
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 2.5.18 Peripheral Frames 0, 1, 2, 3 (PFn) The device segregates peripherals into four sections.
PAGE 38
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com 2.5.20 32-Bit CPU-Timers (0, 1, 2) CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The timers have a 32-bit count-down register, which generates an interrupt when the counter reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
PAGE 39
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 2.5.22 Serial Port Peripherals The devices support the following serial communication peripherals: SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate.
PAGE 40
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 2.6 www.ti.com Register Map The devices contain four peripheral register spaces. The spaces are categorized as follows: Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus. See Table 2-8. Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See Table 2-9.
PAGE 41
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Table 2-9.
PAGE 42
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 2.7 www.ti.com Device Emulation Registers These registers are used to control the protection mode of the C28x CPU and to monitor some critical device signals. The registers are defined in Table 2-12. Table 2-12.
PAGE 43
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Table 2-12.
PAGE 44
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 2.8 www.ti.com VREG, BOR, POR Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip voltage regulator (VREG) to generate the VDD voltage from the VDDIO supply. This eliminates the cost and space of a second external regulator on an application board.
PAGE 45
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 In I/O Pin Out (Force Hi-Z When High) DIR (0 = Input, 1 = Output) SYSRS Internal Weak PU SYSCLKOUT Deglitch Filter XRS Sync RS MCLKRS PLL + Clocking Logic XRS Pin C28 Core JTAG TCK Detect Logic VREGHALT (A) WDRST (B) PBRS A. B.
PAGE 46
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 2.9 www.ti.com System Control This section describes the oscillator and clocking mechanisms, the watchdog function and the low power modes. Table 2-13.
PAGE 47
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Figure 2-11 shows the various clock domains that are discussed. Figure 2-12 shows the various clock sources (both internal and external) that can provide a clock for device operation.
PAGE 48
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.
PAGE 49
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 2.9.1 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Internal Zero Pin Oscillators The F2806x devices contain two independent internal zero pin oscillators. By default both oscillators are turned on at power up, and internal oscillator 1 is the default clock source at this time. For power savings, unused oscillators may be powered down by the user.
PAGE 50
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 2.9.3 www.ti.com PLL-Based Clock Module The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 5-bit ratio control PLLCR[DIV] to select different CPU clock rates.
PAGE 51
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 The PLL-based clock module provides four modes of operation: • INTOSC1 (Internal Zero-pin Oscillator 1): This is the on-chip internal oscillator 1. This can provide the clock for the Watchdog block, core and CPU-Timer 2 • INTOSC2 (Internal Zero-pin Oscillator 2): This is the on-chip internal oscillator 2.
PAGE 52
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 2.9.4 www.ti.com USB and HRCAP PLL Module (PLL2) In addition to the main system PLL, these devices also contain a second PLL (PLL2) which can be used to clock the USB and HRCAP peripherals. The PLL supports multipliers of 1 to 15 and has a fixed divide-bytwo on its output.
PAGE 53
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 2.9.5 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Loss of Input Clock (NMI Watchdog Function) The 2806x devices may be clocked from either one of the internal zero-pin oscillators (INTOSC1/INTOSC2), the on-chip crystal oscillator, or from an external clock input.
PAGE 54
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com Normally, when the input clocks are present, the CPU-watchdog counter decrements to initiate a CPUwatchdog reset or WDINT interrupt. However, when the external input clock fails, the CPU-watchdog counter stops decrementing (that is, the watchdog counter does not change with the limp-mode clock).
PAGE 55
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 2.10 Low-power Modes Block Table 2-18 summarizes the various modes. Table 2-18.
PAGE 56
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com 3 Device and Documentation Support 3.1 Getting Started This section gives a brief overview of the steps to take when first developing for a C28x device. For more detail on each of these steps, see the following: • Getting Started With TMS320C28x Digital Signal Controllers (literature number SPRAAM0).
PAGE 57
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.
PAGE 58
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 3.4 www.ti.com Documentation Support Extensive documentation supports all of the TMS320™ MCU family generations of devices from product announcement through applications development. The types of documentation available include: data sheets and data manuals, with design specifications; and hardware and software applications.
PAGE 59
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 3.5 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E Community TI's Engineer-to-Engineer (E2E) Community.
PAGE 60
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com 4 Device Operating Conditions 4.1 Absolute Maximum Ratings (1) (2) Supply voltage range, VDDIO (I/O and Flash) with respect to VSS –0.3 V to 4.6 V Supply voltage range, VDD with respect to VSS –0.3 V to 2.5 V Analog voltage range, VDDA with respect to VSSA –0.3 V to 4.6 V Input voltage range, VIN (3.3 V) –0.3 V to 4.
PAGE 61
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 4.3 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Electrical Characteristics (1) over recommended operating conditions (unless otherwise noted) PARAMETER VOH High-level output voltage VOL Low-level output voltage IIL IIH Input current (low level) Input current (high level) TEST CONDITIONS IOH = IOH MAX MIN MAX UNIT 2.4 IOH = 50 μA V VDDIO – 0.2 IOL = IOL MAX 0.
PAGE 62
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com 5 Peripheral and Electrical Specifications 5.1 Parameter Information 5.1.1 Timing Parameter Symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: 5.1.
PAGE 63
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 5.3 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Device Clock Table This section provides the timing requirements and switching characteristics for the various clock options available on the 2806x MCUs. Table 5-1 lists the cycle times of various clocks. Table 5-1.
PAGE 64
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com Table 5-3. Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics PARAMETER MIN TYP MAX UNIT Internal zero-pin oscillator 1 (INTOSC1) at 30°C (1) (2) Frequency 10.000 MHz Internal zero-pin oscillator 2 (INTOSC2) at 30°C (1) (2) Frequency 10.
PAGE 65
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 5.4 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Clock Requirements and Characteristics Table 5-4. XCLKIN Timing Requirements - PLL Enabled NO.
PAGE 66
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 5.5 www.ti.com Power Sequencing There is no power sequencing requirement needed to ensure the device is in the proper state after reset or to prevent the I/Os from glitching during power up or power down (GPIO19, GPIO26–27, GPIO34–38 do not have glitch-free I/Os). No voltage larger than a diode drop (0.
PAGE 67
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Table 5-7. Reset (XRS) Timing Requirements MIN th(boot-mode) Hold time for boot-mode pins tw(RSL2) Pulse duration, XRS low on warm reset MAX UNIT 1000tc(SCO) cycles 32tc(OSCCLK) cycles Table 5-8.
PAGE 68
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com Figure 5-6 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR = 0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2.
PAGE 69
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 5.6 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Current Consumption Table 5-9.
PAGE 70
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com NOTE The peripheral - I/O multiplexing implemented in the device prevents all available peripherals from being used at the same time. This is because more than one peripheral function may share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although such a configuration is not useful.
PAGE 71
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 5.6.1 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Reducing Current Consumption The 2806x devices incorporate a method to reduce the device current consumption. Since each peripheral unit has an individual clock-enable bit, significant reduction in current consumption can be achieved by turning off the clock to any peripheral module that is not used in a given application.
PAGE 72
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com Following are other methods to reduce power consumption further: • The flash module may be powered down if code is run off SARAM. This results in a current reduction of 18 mA (typical) in the VDD rail and 13 mA (typical) in the VDDIO rail. • Savings in IDDIO may be realized by disabling the pullups on pins that assume an output function.
PAGE 73
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 5.7 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Emulator Connection Without Signal Buffering for the MCU Figure 5-9 shows the connection between the MCU and JTAG header for a single-processor configuration. If the distance between the JTAG header and the MCU is greater than 6 inches, the emulation signals must be buffered.
PAGE 74
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 5.8 www.ti.com Interrupts Figure 5-10 shows how the various interrupt sources are multiplexed.
PAGE 75
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts per group equals 96 possible interrupts. Table 5-11 shows the interrupts used by 2806x devices.
PAGE 76
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com Table 5-11. PIE MUXed Peripheral Interrupt Vector Table (1) INT1.y INT2.y INT3.y INT4.y INT5.y INT6.y INT7.y INT8.y INT9.y INT10.y INT11.y INT12.y (1) 76 INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 WAKEINT TINT0 ADCINT9 XINT2 XINT1 Reserved ADCINT2 ADCINT1 (LPM/WD) (TIMER 0) (ADC) Ext. int.
PAGE 77
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Table 5-12.
PAGE 78
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 5.8.1 www.ti.com External Interrupts Table 5-13.
PAGE 79
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com 5.9 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Control Law Accelerator (CLA) Overview The control law accelerator extends the capabilities of the C28x CPU by adding parallel processing. Timecritical control loops serviced by the CLA can achieve low ADC sample to output delay. Thus, the CLA enables faster system response and higher frequency control loops.
PAGE 80
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.
PAGE 81
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Table 5-16.
PAGE 82
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com 5.10 Analog Block A 12-bit ADC core is implemented that has different timings than the 12-bit ADC used on the F280x and F2833x devices. The ADC wrapper is modified to incorporate the new timings and also other enhancements to improve the timing control of start of conversions.
PAGE 83
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 5.10.1 Analog-to-Digital Converter (ADC) 5.10.1.1 Features The core of the ADC contains a single 12-bit converter fed by two sample-and-hold circuits. The sampleand-hold circuits can be sampled simultaneously or sequentially. These, in turn, are fed by a total of up to 16 analog input channels.
PAGE 84
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com Table 5-18.
PAGE 85
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.
PAGE 86
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com 5.10.1.2 ADC Start-of-Conversion Electrical Data/Timing Table 5-20. External ADC Start-of-Conversion Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER tw(ADCSOCL) MIN Pulse duration, ADCSOCxO low MAX 32tc(HCO ) UNIT cycles tw(ADCSOCL) ADCSOCAO or ADCSOCBO Figure 5-16.
PAGE 87
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Table 5-22.
PAGE 88
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 ADCIN Rs Source Signal www.ti.com Ron 3.4 kW Switch Cp 5 pF ac Ch 1.6 pF 28x DSP Typical Values of the Input Circuit Components: Switch Resistance (Ron): 3.4 k W Sampling Capacitor (Ch): 1.6 pF Parasitic Capacitance (Cp): 5 pF Source Resistance (Rs): 50 W Figure 5-18.
PAGE 89
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 5.10.1.3.3 ADC Sequential and Simultaneous Timings Analog Input SOC0 Sample Window 0 2 SOC1 Sample Window 9 15 SOC2 Sample Window 22 24 37 ADCCLK ADCCTL 1.INTPULSEPOS ADCSOCFLG 1.SOC0 ADCSOCFLG 1.SOC1 ADCSOCFLG 1.
PAGE 90
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com Analog Input SOC0 Sample Window 0 2 SOC1 Sample Window 9 15 SOC2 Sample Window 22 24 37 ADCCLK ADCCTL1.INTPULSEPOS ADCSOCFLG 1.SOC0 ADCSOCFLG 1.SOC1 ADCSOCFLG 1.SOC2 S/H Window Pulse to Core SOC0 SOC1 SOC2 Result 0 Latched ADCRESULT 0 ADCRESULT 1 EOC0 Pulse EOC1 Pulse EOC2 Pulse ADCINTFLG .
PAGE 91
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Analog Input A SOC0 Sample A Window SOC2 Sample A Window SOC0 Sample B Window SOC2 Sample B Window Analog Input B 0 2 9 22 24 37 50 ADCCLK ADCCTL1.INTPULSEPOS ADCSOCFLG 1.SOC0 ADCSOCFLG 1.SOC1 ADCSOCFLG 1.
PAGE 92
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com Analog Input A SOC0 Sample A Window SOC2 Sample A Window SOC0 Sample B Window SOC2 Sample B Window Analog Input B 0 9 2 22 24 37 50 ADCCLK ADCCTL1.INTPULSEPOS ADCSOCFLG1.SOC0 ADCSOCFLG1.SOC1 ADCSOCFLG1.
PAGE 93
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 5.10.2 ADC MUX To COMPy A or B input To ADC Channel X Logic implemented in GPIO MUX block AIOx Pin SYSCLK AIOxIN 1 AIOxINE AIODAT Reg (Read) SYNC 0 AIODAT Reg (Latch) AIOxDIR (1 = Input, 0 = Output) AIOMUX 1 Reg AIOSET, AIOCLEAR, AIOTOGGLE Regs AIODIR Reg (Latch) 1 (0 = Input, 1 = Output) 0 0 Figure 5-23.
PAGE 94
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com 5.10.3 Comparator Block Figure 5-24 shows the interaction of the Comparator modules with the rest of the system. COMP x A COMP x B + COMP - GPIO MUX COMP x + DAC x Wrapper AIO MUX TZ1/2/3 ePWM COMPxOUT DAC Core 10-Bit Figure 5-24. Comparator Block Diagram Table 5-25.
PAGE 95
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 5.10.3.1 On-Chip Comparator/DAC Electrical Data/Timing Table 5-26.
PAGE 96
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com 5.11 Detailed Descriptions Integral Nonlinearity Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. The point used as zero occurs one-half LSB before the first code transition. The full-scale point is defined as level one-half LSB beyond the last code transition.
PAGE 97
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 5.12 Serial Peripheral Interface (SPI) Module The device includes the four-pin serial peripheral interface (SPI) module. Up to two SPI modules are available.
PAGE 98
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com The SPI port operation is configured and controlled by the registers listed in Table 5-27 and Table 5-28. Table 5-27.
PAGE 99
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Figure 5-26 is a block diagram of the SPI in slave mode. SPIFFENA SPIFFTX.14 Receiver Overrun Flag RX FIFO Registers SPISTS.7 Overrun INT ENA SPICTL.4 SPIRXBUF RX FIFO _0 RX FIFO _1 ----- SPIINT RX FIFO Interrupt RX FIFO _3 RX Interrupt Logic 16 SPIRXBUF Buffer Register SPIFFOVF FLAG SPIFFRX.
PAGE 100
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com Table 5-29. SPI Master Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5) SPI WHEN (SPIBRR + 1) IS EVEN OR SPIBRR = 0 OR 2 NO.
PAGE 101
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 4 5 SPISIMO Master Out Data Is Valid 8 9 SPISOMI Master In Data Must Be Valid (A) SPISTE A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.
PAGE 102
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com Table 5-30. SPI Master Mode External Timing (Clock Phase = 1) (1) (2) (3) (4) (5) SPI WHEN (SPIBRR + 1) IS EVEN OR SPIBRR = 0 OR 2 NO.
PAGE 103
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 6 7 SPISIMO Master out data Is valid Data Valid 10 11 SPISOMI Master in data must be valid SPISTE(A) A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.
PAGE 104
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com 5.12.2 Serial Peripheral Interface (SPI) Slave Mode Electrical Data/Timing Table 5-31 lists the slave mode external timing (clock phase = 0) and Table 5-32 lists the slave mode external timing (clock phase = 1). Figure 5-29 and Figure 5-30 show the timing waveforms. Table 5-31.
PAGE 105
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Table 5-32. SPI Slave Mode External Timing (Clock Phase = 1) (1) (2) (3) (4) (5) NO. MIN MAX 12 tc(SPC)S Cycle time, SPICLK 13 tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 0.
PAGE 106
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com 5.13 Serial Communications Interface (SCI) Module The devices include two serial communications interface (SCI) modules (SCI-A, SCI-B). The SCI module supports digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format.
PAGE 107
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 The SCI port operation is configured and controlled by the registers listed in Table 5-33 and Table 5-34. Table 5-33.
PAGE 108
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com Figure 5-31 shows the SCI module block diagram. SCICTL1.1 SCITXD Frame Format and Mode TXSHF Register Parity Even/Odd Enable TXENA 8 SCICCR.6 SCICCR.5 TXRDY Transmitter-Data Buffer Register TXWAKE SCICTL1.3 8 TX INT ENA SCICTL2.7 SCICTL2.
PAGE 109
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 5.
PAGE 110
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com Figure 5-32 shows the block diagram of the McBSP module.
PAGE 111
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Table 5-35 provides a summary of the McBSP registers. Table 5-35.
PAGE 112
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com 5.14.1 Multichannel Buffered Serial Port (McBSP) Electrical Data/Timing 5.14.1.1 McBSP Transmit and Receive Timing Table 5-36. McBSP Timing Requirements (1) (2) NO.
PAGE 113
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Table 5-37. McBSP Switching Characteristics (1) (2) over recommended operating conditions (unless otherwise noted) NO.
PAGE 114
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com M1, M11 M2, M12 M13 M3, M12 CLKR M4 M4 M14 FSR (int) M15 M16 FSR (ext) M18 M17 DR (RDATDLY=00b) Bit (n−1) (n−2) (n−3) M17 (n−4) M18 DR (RDATDLY=01b) Bit (n−1) (n−2) M17 (n−3) M18 DR (RDATDLY=10b) Bit (n−1) (n−2) Figure 5-33.
PAGE 115
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 5.14.1.2 McBSP as SPI Master or Slave Timing Table 5-38. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) NO.
PAGE 116
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com Table 5-40. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) MASTER NO.
PAGE 117
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Table 5-42. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) NO.
PAGE 118
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com Table 5-44. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) MASTER NO.
PAGE 119
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 5.15 Enhanced Controller Area Network (eCAN) Module The CAN module (eCAN-A) has the following features: • Fully compliant with CAN protocol, version 2.
PAGE 120
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 eCAN0INT eCAN1INT www.ti.
PAGE 121
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.
PAGE 122
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com The CAN registers listed in Table 5-47 are used by the CPU to configure and control the CAN controller and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary. Table 5-47.
PAGE 123
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 5.16 Inter-Integrated Circuit (I2C) The device contains one I2C Serial Port. Figure 5-41 shows how the I2C peripheral module interfaces within the device. The I2C module has the following features: • Compliance with the Philips Semiconductors I2C-bus specification (version 2.
PAGE 124
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com I2C Module I2CXSR I2CDXR TX FIFO FIFO Interrupt to CPU/PIE SDA RX FIFO Peripheral Bus I2CRSR SCL I2CDRR Clock Synchronizer Control/Status Registers CPU Prescaler Noise Filters Interrupt to CPU/PIE I2C INT Arbitrator A. B. The I2C registers are accessed at the SYSCLKOUT rate.
PAGE 125
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 5.16.1 Inter-Integrated Circuit (I2C) Electrical Data/Timing Table 5-49.
PAGE 126
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com 5.17 Enhanced Pulse Width Modulator (ePWM) Modules (ePWM1–ePWM8) The devices contain up to eight enhanced PWM Modules (ePWM). Figure 5-42 shows a block diagram of multiple ePWM modules. Figure 5-43 shows the signal interconnections with the ePWM. Table 5-50 and Table 5-51 show the complete ePWM register set per module.
PAGE 127
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Table 5-50.
PAGE 128
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com Table 5-50.
PAGE 129
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Table 5-51.
PAGE 130
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com Table 5-51.
PAGE 131
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.
PAGE 132
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com 5.17.1 Enhanced Pulse Width Modulator (ePWM) Electrical Data/Timing PWM refers to PWM outputs on ePWM1–8. Table 5-52 shows the PWM timing requirements and Table 553, switching characteristics. Table 5-52.
PAGE 133
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 5.18 High-Resolution PWM (HRPWM) This module combines multiple delay lines in a single module and a simplified calibration system by using a dedicated calibration delay line. For each ePWM module there is one HR delay line.
PAGE 134
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com 5.19 Enhanced Capture Module (eCAP1) SYNC The device contains an enhanced capture (eCAP) module. Figure 5-45 shows a functional block diagram of a module.
PAGE 135
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Table 5-56.
PAGE 136
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com 5.20 High-Resolution Capture Modules (HRCAP1–HRCAP4) The device contains up to four high-resolution capture (HRCAP) modules. The High-Resolution Capture (HRCAP) module measures the difference between external pulses with a typical resolution of 300 ps.
PAGE 137
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Table 5-59.
PAGE 138
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com 5.21 Enhanced Quadrature Encoder Modules (eQEP1, eQEP2) The device contains up to two enhanced quadrature encoder (eQEP) modules. Table 5-61 provides a summary of the eQEP registers. Table 5-61.
PAGE 139
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Figure 5-47 shows the block diagram of the eQEP module.
PAGE 140
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 5.21.1 www.ti.com Enhanced Quadrature Encoder (eQEP) Electrical Data/Timing Table 5-62 shows the eQEP timing requirement and Table 5-63 shows the eQEP switching characteristics. Table 5-62.
PAGE 141
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 5.22 JTAG Port On the 2806x device, the JTAG port is reduced to 5 pins (TRST, TCK, TDI, TMS, TDO). TCK, TDI, TMS and TDO pins are also GPIO pins. The TRST signal selects either JTAG or GPIO operating mode for the pins in Figure 5-48. During emulation/debug, the GPIO function of these pins are not available.
PAGE 142
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com 5.23 General-Purpose Input/Output (GPIO) MUX The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to providing individual pin bit-banging I/O capability. The device supports 45 GPIO pins.
PAGE 143
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Table 5-65.
PAGE 144
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com Table 5-66.
PAGE 145
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Table 5-67.
PAGE 146
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.
PAGE 147
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 5.23.1 General-Purpose Input/Output (GPIO) Electrical Data/Timing 5.23.1.1 GPIO Output Timing Table 5-68.
PAGE 148
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com 5.23.1.2 GPIO Input Timing Table 5-69.
PAGE 149
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 5.23.1.3 Sampling Window Width for Input Signals The following section summarizes the sampling window width for input signals for various input qualifier configurations. Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
PAGE 150
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com 5.23.1.4 Low-Power Mode Wakeup Timing Table 5-70 shows the timing requirements, Table 5-71 shows the switching characteristics, and Figure 554 shows the timing diagram for IDLE mode. Table 5-70.
PAGE 151
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 Table 5-72. STANDBY Mode Timing Requirements MIN tw(WAKE-INT) (1) Pulse duration, external wake-up signal Without input qualification With input qualification (1) MAX 3tc(OSCCLK) UNIT cycles (2 + QUALSTDBY) * tc(OSCCLK) QUALSTDBY is a 6-bit field in the LPMCR0 register. Table 5-73.
PAGE 152
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com (C) (A) (B) Device Status (F) (D)(E) STANDBY (G) STANDBY Normal Execution Flushing Pipeline Wake-up (H) Signal tw(WAKE-INT) td(WAKE-STBY) X1/X2 or XCLKIN XCLKOUT td(IDLE−XCOL) A. B. C. D. E. F. G. H. IDLE instruction is executed to put the device into STANDBY mode. The PLL block responds to the STANDBY signal.
PAGE 153
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 (C) (A) (F) (B) Device Status HALT Flushing Pipeline (H) (G) (D)(E) HALT PLL Lock-up Time Wake-up Latency Normal Execution (I) GPIOn td(WAKE−HALT ) tw(WAKE-GPIO) tp X1/X2 or XCLKIN Oscillator Start-up Time XCLKOUT td(IDLE−XCOL) A. B. C. D. E. F. G. H. I. IDLE instruction is executed to put the device into HALT mode.
PAGE 154
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com 5.24 Universal Serial Bus (USB) 5.24.1 Universal Serial Bus (USB) Electrical Data/Timing Table 5-76. USB Input Ports DP and DM Timing Requirements VCC MIN MAX 2.5 UNIT V(CM) Differential input common mode range 0.8 Z(IN) Input impedance 300 V VCRS Crossover voltage 1.3 VIL Static SE input logic-low level 0.
PAGE 155
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 5.25 Flash Timing Table 5-78.
PAGE 156
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 www.ti.com Table 5-83. Flash Data Retention Duration PARAMETER tretention TEST CONDITIONS Data retention duration TJ = 55°C MIN MAX 15 UNIT years Table 5-84. Minimum Required Flash/OTP Wait-States at Different Frequencies (1) SYSCLKOUT (MHz) SYSCLKOUT (ns) PAGE WAIT-STATE (1) RANDOM WAIT-STATE (1) OTP WAIT-STATE 90 11.
PAGE 157
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 6 Revision History This data sheet revision history highlights the technical changes made to the SPRS698C device-specific data sheet to make it an SPRS698D revision. Scope: The TMS320F2806xU devices are now "TMS" devices (fully qualified production devices). See Section 3.3 for more information on device status.
PAGE 158
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 LOCATION www.ti.com ADDITIONS, DELETIONS, AND MODIFICATIONS Table 5-11 PIE MUXed Peripheral Interrupt Vector Table: • (INTx.8, INT5.
PAGE 159
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 www.ti.com SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 7 Mechanical Packaging and Orderable Information 7.1 Thermal Data Table 7-1 through Table 7-4 show the thermal data. See Section 7.1.1 for more information on thermal design considerations. Table 7-1. Thermal Model 100-Pin PZP Results AIR FLOW PARAMETER 0 lfm 150 lfm 250 lfm 500 lfm θJA [°C/W] High k PCB 24.4 15.1 13.9 12.
PAGE 160
TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012 7.1.1 www.ti.com Thermal Design Considerations Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems that exceed the recommended maximum power dissipation in the end product may require additional thermal enhancements. Ambient temperature (TA) varies with the end application and product design.
PAGE 161
MECHANICAL DATA MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996 PN (S-PQFP-G80) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 41 60 61 40 80 21 0,13 NOM 1 20 Gage Plane 9,50 TYP 12,20 SQ 11,80 14,20 SQ 13,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040135 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
PAGE 162
MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 75 0,08 M 51 76 50 100 26 1 0,13 NOM 25 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,05 MIN 1,45 1,35 0,25 0°– 7° 0,75 0,45 Seating Plane 0,08 1,60 MAX 4040149 /B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
PAGE 163
PAGE 164
PAGE 165
PAGE 166
PAGE 167
PAGE 168
PACKAGE OPTION ADDENDUM www.ti.
PAGE 169
PACKAGE OPTION ADDENDUM www.ti.
PAGE 170
PACKAGE OPTION ADDENDUM www.ti.
PAGE 171
PACKAGE OPTION ADDENDUM www.ti.
PAGE 172
PACKAGE OPTION ADDENDUM www.ti.com 5-Dec-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
PAGE 173
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.