Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller BGA 176 (15x15) 32-Bit 150 MHz I/O number 88

TMS320F28335, TMS320F28334, TMS320F28332

TMS320F28235, TMS320F28234, TMS320F28232

Digital Signal Controllers (DSCs)

Data Manual

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Literature Number: SPRS439M

June 2007–Revised August 2012

Summary of content (199 pages)

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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 Digital Signal Controllers (DSCs) Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Contents 1 TMS320F2833x, TMS320F2823x DSCs 1.1 1.2 2 Introduction 2.1 2.2 3 3.3 3.4 3.5 3.6 3.7 4 .......................................................................................................... 33 Memory Maps .............................................................................................................. Brief Descriptions ...............
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com 4.8 4.9 4.10 4.11 4.12 4.13 4.14 5 4.7.2 ADC Registers .................................................................................................. 82 4.7.3 ADC Calibration ................................................................................................. 83 Multichannel Buffered Serial Port (McBSP) Module ..................................................................
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 6.15 6.16 6.17 6.18 www.ti.com 6.14.7 External Interface Ready-on-Read Timing With One External Wait State ............................ 6.14.8 External Interface Ready-on-Write Timing With One External Wait State ............................. 6.14.9 XHOLD and XHOLDA Timing ...............................................................................
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 List of Figures 2-1 F2833x, F2823x 176-Pin PGF/PTP LQFP (Top View) ......................................................................
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com ............................................................. 6-3 Emulator Connection Without Signal Buffering for the DSP 6-4 3.3-V Test Load Circuit......................................................................................................... 124 6-5 Clock Timing ...........................................................................................
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 List of Tables .................................................................................................... 12 .................................................................................................... 13 Signal Descriptions ...............................................................................................................
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com 6-5 Clocking and Nomenclature (100-MHz Devices) ........................................................................... 125 6-6 Input Clock Frequency .........................................................................................................
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 6-53 Sequential Sampling Mode Timing ........................................................................................... 172 6-54 ....................................................................................... McBSP Timing Requirements ................................................................................................
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Digital Signal Controllers (DSCs) Check for Samples: TMS320F28335, TMS320F28334, TMS320F28332, TMS320F28235, TMS320F28234, TMS320F28232 1 TMS320F2833x, TMS320F2823x DSCs 1.1 Features 123 • High-Performance Static CMOS Technology – Up to 150 MHz (6.67-ns Cycle Time) – 1.9-V/1.8-V Core, 3.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 • Low-Power Modes and Power Savings – IDLE, STANDBY, HALT Modes Supported – Disable Individual Peripheral Clocks • Endianness: Little Endian • Package Options: – Lead-free, Green Packaging – Low-Profile Quad Flatpack (PGF, PTP) – MicroStar BGA™ (ZHH) – Plastic BGA (ZJZ) 1.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 2 www.ti.com Introduction The TMS320F28335, TMS320F28334, TMS320F28332, TMS320F28235, TMS320F28234, and TMS320F28232 devices, members of the TMS320C28x™/ Delfino™ DSC/MCU generation, are highly integrated, high-performance solutions for demanding control applications.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Table 2-1. F2833x Hardware Features (continued) FEATURE TYPE (1) F28335 (150 MHz) F28334 (150 MHz) F28332 (100 MHz) – TMS TMS TMS Product status (2) (2) See Section 5.1, Device and Development Support Tool Nomenclature, for descriptions of device stages. Table 2-2.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 2.1 www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com 2.2 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Signal Descriptions Table 2-3 describes the signals. The GPIO function (shown in Italics) is the default at reset. The peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. See Table 2-1 and Table 2-2 for details. Inputs are not 5-V tolerant.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Table 2-3. Signal Descriptions (continued) PIN NO. NAME PGF, PTP PIN # ZHH BALL # DESCRIPTION ZJZ BALL # (1) CLOCK XCLKOUT 138 C11 A10 Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Table 2-3. Signal Descriptions (continued) PIN NO. NAME ADCREFP ADCREFM PGF, PTP PIN # 56 55 ZHH BALL # P5 N5 DESCRIPTION ZJZ BALL # (1) P5 Internal Reference Positive Output. Requires a low ESR (under 1.5 Ω) ceramic bypass capacitor of 2.2 μF to analog ground.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Table 2-3. Signal Descriptions (continued) PIN NO.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Table 2-3. Signal Descriptions (continued) PIN NO.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Table 2-3. Signal Descriptions (continued) PIN NO.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Table 2-3. Signal Descriptions (continued) PIN NO.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Table 2-3. Signal Descriptions (continued) PIN NO.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Table 2-3. Signal Descriptions (continued) PIN NO.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Table 2-3. Signal Descriptions (continued) PIN NO.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 3.1 www.ti.com Memory Maps In Figure 3-2 through Figure 3-4, the following apply: • Memory blocks are not to scale. • Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps are restricted to data memory only. A user program cannot access these memory maps in program space.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Block Start Address www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Table 3-1.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 NOTE • When the code-security passwords are programmed, all addresses between 0x33FF80 and 0x33FFF5 cannot be used as program code or data. These locations must be programmed to 0x0000. • If the code security feature is not used, addresses 0x33FF80 through 0x33FFEF may be used for code or data.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com The wait-states for the various spaces in the memory map area are listed in Table 3-5. Table 3-5.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com 3.2 3.2.1 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Brief Descriptions C28x CPU The F2833x (C28x+FPU)/F2823x (C28x) family is a member of the TMS320C2000™ digital signal controller (DSC) platform. The C28x+FPU based controllers have the same 32-bit fixed-point architecture as TI's existing C28x DSCs, but also include a single-precision (32-bit) IEEE 754 floating-point unit (FPU).
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 3.2.4 www.ti.com Real-Time JTAG and Analysis The 2833x/2823x devices implement the standard IEEE 1149.1 JTAG interface. Additionally, the devices support real-time mode of operation whereby the contents of memory, peripheral and register locations can be modified while the processor is running and executing code and servicing interrupts.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com 3.2.8 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 L0, L1, L2, L3, L4, L5, L6, L7 SARAMs The F28335/F28235 and F28334/F28234 each contain 32K × 16 of single-access RAM, divided into 8 blocks (L0–L7 with 4K each). The F28332/F28232 contain 24K × 16 of single-access RAM, divided into 6 blocks (L0–L5 with 4K each). Each block can be independently accessed to minimize CPU pipeline stalls.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 3.2.9.1 www.ti.com Peripheral Pins Used by the Bootloader Table 3-7 shows which GPIO pins are used by each peripheral bootloader. Refer to the GPIO mux table to see if these conflict with any of the peripherals you would like to use in your application. Table 3-7.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 NOTE • When the code-security passwords are programmed, all addresses between 0x33FF80 and 0x33FFF5 cannot be used as program code or data. These locations must be programmed to 0x0000. • If the code security feature is not used, addresses 0x33FF80 through 0x33FFEF may be used for code or data.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com 3.2.11 Peripheral Interrupt Expansion (PIE) Block The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block can support up to 96 peripheral interrupts. On the 2833x/2823x, 58 of the possible 96 interrupts are used by peripherals.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 3.2.17 Peripheral Frames 0, 1, 2, 3 (PFn) The device segregates peripherals into four sections.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com 3.2.20 Control Peripherals The 2833x/2823x devices support the following peripherals which are used for embedded control and communication: ePWM: The enhanced PWM peripheral supports independent and complementary PWM generation, adjustable dead-band generation for leading and trailing edges, latched and cycle-by-cycle trip mechanism.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com 3.3 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Register Map The devices contain four peripheral register spaces. The spaces are categorized as follows: Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus. See Table 3-8. Peripheral Frame 1 These are peripherals that are mapped to the 32-bit peripheral bus. See Table 3-9.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Table 3-10.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com 3.4 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Device Emulation Registers These registers are used to control the protection mode of the C28x CPU and to monitor some critical device signals. The registers are defined in Table 3-12. Table 3-12.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 3.5 www.ti.com Interrupts Figure 3-5 shows how the various interrupt sources are multiplexed.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com IFR(12:1) INTM IER(12:1) INT1 INT2 1 CPU MUX 0 INT11 INT12 (Flag) Global Enable (Enable) INTx.1 INTx.2 INTx INTx.3 INTx.4 MUX INTx.5 INTx.6 From Peripherals or External Interrupts INTx.7 PIEACKx INTx.8 (Enable) (Flag) PIEIERx(8:1) PIEIFRx(8:1) (Enable/Flag) Figure 3-7. Multiplexing of Interrupts Using the PIE Block Table 3-13.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Table 3-14.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 3.5.1 www.ti.com External Interrupts Table 3-15.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com 3.6 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 System Control This section describes the oscillator, PLL and clocking mechanisms, the watchdog function and the low power modes. Figure 3-8 shows the various clock and reset domains that will be discussed.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in Table 3-16. Table 3-16.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 The three possible input-clock configurations are shown in Figure 3-10 through Figure 3-12. XCLKIN X1 X2 NC External Clock Signal (Toggling 0-VDDIO) Figure 3-10. Using a 3.3-V External Oscillator XCLKIN X1 X2 External Clock Signal (Toggling 0-VDD) NC Figure 3-11. Using a 1.9-V External Oscillator X1 XCLKIN X2 CL2 CL1 Crystal Figure 3-12.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 3.6.1.2 www.ti.com PLL-Based Clock Module The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Table 3-19. Possible PLL Configuration Modes REMARKS PLLSTS[DIVSEL] CLKIN AND SYSCLKOUT PLL Off Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block is disabled in this mode. This can be useful to reduce system noise and for low power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass) before entering this mode.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 3.6.2 www.ti.com Watchdog Block The watchdog block on the 2833x/2823x device is similar to the one used on the 240x and 281x devices. The watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8bit watchdog up counter has reached its maximum value.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com 3.7 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Low-Power Modes Block The low-power modes on the 2833x/2823x devices are similar to the 240x devices. Table 3-20 summarizes the various modes. Table 3-20.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 4 www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 4.2 www.ti.com 32-Bit CPU-Timer 0, CPU-Timer 1, CPU-Timer 2 There are three 32-bit CPU-timers on the devices (CPU-Timer 0, CPU-Timer 1, CPU-Timer 2). Timer 2 is reserved for DSP/BIOS™. CPU-Timer 0 and CPU-Timer 1 can be used in user applications. These timers are different from the timers that are present in the ePWM modules.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 The general operation of the timer is as follows: The 32-bit counter register "TIMH:TIM" is loaded with the value in the period register "PRDH:PRD". The counter register decrements at the SYSCLKOUT rate of the C28x. When the counter reaches 0, a timer interrupt output signal generates an interrupt pulse. The registers listed in Table 4-1 are used to configure the timers.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 4.3 www.ti.com Enhanced PWM Modules The 2833x/2823x devices contain up to six enhanced PWM (ePWM) modules (ePWM1, ePWM2, ePWM3, ePWM4, ePWM5, ePWM6). Figure 4-4 shows the time-base counter synchronization scheme 3. Figure 45 shows the signal interconnections with the ePWM.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Table 4-2.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Table 4-3.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 4.4 www.ti.com High-Resolution PWM (HRPWM) The HRPWM module offers PWM resolution (time granularity) which is significantly better than what can be achieved using conventionally derived digital PWM methods.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com 4.5 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Enhanced CAP Modules The 2833x/2823x device contains up to six enhanced capture (eCAP) modules (eCAP1, eCAP2, eCAP3, eCAP4, eCAP5, and eCAP6). Figure 4-6 shows a functional block diagram of a module.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com The eCAP modules are clocked at the SYSCLKOUT rate. The clock enable bits (ECAP1ENCLK, ECAP2ENCLK, ECAP3ENCLK, ECAP4ENCLK, ECAP5ENCLK, ECAP6ENCLK) in the PCLKCR1 register are used to turn off the eCAP modules individually (for low power operation).
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com 4.6 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Enhanced QEP Modules The device contains up to two enhanced quadrature encoder (eQEP) modules (eQEP1, eQEP2). Figure 47 shows the block diagram of the eQEP module.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Table 4-5 provides a summary of the eQEP registers. Table 4-5.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com 4.7 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Analog-to-Digital Converter (ADC) Module A simplified functional block diagram of the ADC module is shown in Figure 4-8. The ADC module consists of a 12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include: • 12-bit ADC core with built-in S/H • Analog input: 0.0 V to 3.0 V (Voltages above 3.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Figure 4-9 shows the ADC pin-biasing for internal reference and Figure 4-10 shows the ADC pin-biasing for external reference.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 ADC 16-Channel Analog Inputs www.ti.com ADCINA[7:0] ADCINB[7:0] ADCLO ADCREFIN ADC External Current Bias Resistor ADCRESEXT ADC Reference Positive Output ADCREFP ADC Reference Medium Output ADCREFM Analog input 0-3 V with respect to ADCLO Connect to Analog Ground (D) Connect to 1.500, 1.024, or 2.048-V precision source 22 k (A) 2.2 μF (A) 2.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com 4.7.1 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 ADC Connections if the ADC Is Not Used It is recommended to keep the connections for the analog power pins, even if the ADC is not used.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 4.7.2 www.ti.com ADC Registers The ADC operation is configured, controlled, and monitored by the registers listed in Table 4-6. Table 4-6.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com 4.7.3 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 ADC Calibration The ADC_cal() routine is programmed into TI reserved OTP memory by the factory. The boot ROM automatically calls the ADC_cal() routine to initialize the ADCREFSEL and ADCOFFTRIM registers with device specific calibration data. During normal operation, this process occurs automatically and no action is required by the user.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Figure 4-11 shows the block diagram of the McBSP module.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Table 4-7 provides a summary of the McBSP registers. Table 4-7.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 4.9 www.ti.com Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B) The CAN module has the following features: • Fully compliant with CAN protocol, version 2.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com The CAN registers listed in Table 4-9 are used by the CPU to configure and control the CAN controller and the message objects. eCAN control registers only support 32-bit read/write operations. Mailbox RAM can be accessed as 16 bits or 32 bits. 32-bit accesses are aligned to an even boundary. Table 4-9.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 4.10 Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C) The devices include three serial communications interface (SCI) modules. The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard nonreturn-to-zero (NRZ) format.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Enhanced features: • Auto baud-detect hardware logic • 16-level transmit/receive FIFO The SCI port operation is configured and controlled by the registers listed in Table 4-10, Table 4-11, and Table 4-12. Table 4-10.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Table 4-12.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Figure 4-15 shows the SCI module block diagram. SCICTL1.1 Frame Format and Mode SCITXD TXSHF Register Parity Even/Odd Enable TX EMPTY SCICTL2.6 8 SCICCR.6 SCICCR.5 TXRDY SCICTL2.7 Transmitter-Data Buffer Register TXWAKE SCICTL1.3 WUT SCICTL2.0 TXINT TX FIFO _0 TX Interrupt Logic ----- TX FIFO _15 TX FIFO Interrupts SCITXBUF.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 4.11 Serial Peripheral Interface (SPI) Module (SPI-A) The device includes the four-pin serial peripheral interface (SPI) module. One SPI module (SPI-A) is available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bittransfer rate.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Enhanced features: • 16-level transmit/receive FIFO • Delayed transmit control The SPI port operation is configured and controlled by the registers listed in Table 4-13 . Table 4-13.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Figure 4-16 is a block diagram of the SPI in slave mode. SPIFFENA Overrun INT ENA Receiver Overrun Flag SPIFFTX.14 RX FIFO registers SPISTS.7 SPICTL.4 SPIRXBUF RX FIFO _0 RX FIFO _1 SPIINT/SPIRXINT RX FIFO Interrupt −−−−− RX Interrupt Logic RX FIFO _15 16 SPIRXBUF Buffer Register SPIFFOVF FLAG SPIFFRX.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com 4.12 Inter-Integrated Circuit (I2C) The device contains one I2C Serial Port. Figure 4-17 shows how the I2C peripheral module interfaces within the device. System Control Block C28x CPU I2CAENCLK SYSRS Control Data[16] SDAA Peripheral Bus SYSCLKOUT Data[16] 2 GPIO MUX I C-A Addr[16] SCLA I2CINT1A I2CINT2A A. B.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com • • • • SPRS439M – JUNE 2007 – REVISED AUGUST 2012 One interrupt that can be used by the CPU.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 The device supports 88 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 4-15 shows the GPIO register mapping. Table 4-15.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Table 4-15. GPIO Registers (continued) NAME ADDRESS SIZE (x16) GPIOXINT6SEL 0x6FE6 1 XINT6 GPIO Input Select Register (GPIO32 to 63) DESCRIPTION GPIOINT7SEL 0x6FE7 1 XINT7 GPIO Input Select Register (GPIO32 to 63) GPIOLPMSEL 0x6FE8 2 LPM GPIO Select Register (GPIO0 to 31) Reserved 0x6FEA – 0x6FFF 22 Table 4-16.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Table 4-17.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Table 4-18.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from four choices: • Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT).
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com 4.14 External Interface (XINTF) This section gives a top-level view of the external interface (XINTF) that is implemented on the 2833x/2823x devices. The XINTF is a non-multiplexed asynchronous bus, similar to the 2812 XINTF. The XINTF is mapped into three fixed zones shown in Figure 4-20 .
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 XINTF External wait-state generator 16-bits XREADY XCLKOUT XZCS0, XZCS6, XZCS7 CS A(19:1) XA(19:1) A(0) XA0/XWE1 OE XRD WE XWE0 D(15:0) XD(15:0) Figure 4-21.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 5 www.ti.com Device Support Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of DSCs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 5.2 www.ti.com Documentation Support Extensive documentation supports all of the TMS320™ DSP family generations of devices from product announcement through applications development. The types of documentation available include: data sheets and data manuals, with design specifications; and hardware and software applications.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 SPRU812 TMS320x2833x, 2823x Analog-to-Digital Converter (ADC) Reference Guide describes how to configure and use the on-chip ADC module, which is a 12-bit pipelined ADC. SPRU949 TMS320x2833x, 2823x DSC External Interface (XINTF) Reference Guide describes the XINTF, which is a nonmultiplexed asynchronous bus, as it is used on the 2833x and 2823x devices.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Tools Guides SPRU513 TMS320C28x Assembly Language Tools v5.0.0 User's Guide describes the assembly language tools (assembler and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the TMS320C28x device. SPRU514 TMS320C28x Optimizing C/C++ Compiler v5.0.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 SPRAA91 TMS320F280x Digital Signal Controller USB Connectivity Using the TUSB3410 USB-toUART Bridge Chip presents hardware connections as well as software preparation and operation of the development system using a simple communication echo program.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 SPRM439 F28234 ZHH BSDL Model SPRM442 F28234 ZJZ BSDL Model SPRM437 F28232 PGF BSDL Model SPRM440 F28232 ZHH BSDL Model SPRM443 F28232 ZJZ BSDL Model www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com 5.3 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 6 www.ti.com Electrical Specifications This section provides the absolute maximum ratings and the recommended operating conditions. 6.1 Absolute Maximum Ratings (1) (2) Unless otherwise noted, the list of absolute maximum ratings are specified over operating temperature ranges. Supply voltage range, VDDIO, VDD3VFL with respect to VSS –0.3 V to 4.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com 6.2 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) Device supply voltage, I/O, VDDIO Device supply voltage CPU, VDD MIN NOM MAX UNIT V 3.135 3.3 3.465 Device operation @ 150 MHz 1.805 1.9 1.995 Device operation @ 100 MHz 1.71 1.8 1.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 6.4 www.ti.com Current Consumption Table 6-1. TMS320F28335/F28235 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT MODE TEST CONDITIONS IDD IDDIO (1) IDD3VFL (2) IDDA18 (3) IDDA33 (4) TYP (5) MAX TYP (5) MAX TYP MAX TYP (5) MAX TYP (5) MAX 290 mA 315 mA 30 mA 50 mA 35 mA 40 mA 30 mA 35 mA 1.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Table 6-2. TMS320F28334/F28234 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT MODE TEST CONDITIONS IDD IDDIO (1) IDD3VFL (2) IDDA18 (3) IDDA33 (4) TYP (5) MAX TYP (5) MAX TYP MAX TYP (5) MAX TYP (5) MAX 290 mA 315 mA 30 mA 50 mA 35 mA 40 mA 30 mA 35 mA 1.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 6.4.1 www.ti.com Reducing Current Consumption The 2833x/2823x DSCs incorporate a method to reduce the device current consumption. Since each peripheral unit has an individual clock-enable bit, reduction in current consumption can be achieved by turning off the clock to any peripheral module that is not used in a given application.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com 6.4.2 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Current Consumption Graphs Current Vs Frequency 350.00 300.00 Current (mA) 250.00 200.00 150.00 100.00 50.00 0.00 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 SYSCLKOUT (MHz) IDD IDDIO IDDA18 IDD3VFL 1.8-V Current 3.3-V Current Figure 6-1.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Device Power Vs SYSCLKOUT 1000.0 900.0 Device Power (mW) 800.0 700.0 600.0 500.0 400.0 300.0 200.0 100.0 0 0 0 0 0 0 15 14 13 12 11 10 90 80 70 60 50 40 30 20 10 0.0 SYSCLKOUT (MHz) Figure 6-2.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com 6.5 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Emulator Connection Without Signal Buffering for the DSP Figure 6-3 shows the connection between the DSP and JTAG header for a single-processor configuration. If the distance between the JTAG header and the DSP is greater than 6 inches, the emulation signals must be buffered. If the distance is less than 6 inches, buffering is typically not needed.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 6.6 www.ti.com Timing Parameter Symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: 6.6.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com 6.6.3 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Device Clock Table This section provides the timing requirements and switching characteristics for the various clock options available. Table 6-4 through Table 6-5 list the cycle times of various clocks. Table 6-4.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 6.7 www.ti.com Clock Requirements and Characteristics Table 6-6. Input Clock Frequency PARAMETER MIN Resonator (X1/X2) fx Crystal (X1/X2) Input clock frequency External oscillator/clock source (XCLKIN or X1 pin) fl TYP MAX UNIT 20 35 20 35 150-MHz device 4 150 100-MHz device 4 100 Limp mode SYSCLKOUT frequency range (with /2 enabled) 1-5 MHz MHz Table 6-7.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 C10 C9 C8 XCLKIN(A) C1 C6 C3 C4 C5 XCLKOUT(B) A. B. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is intended to illustrate the timing parameters only and may differ based on actual configuration. XCLKOUT configured to reflect SYSCLKOUT. Figure 6-5. Clock Timing 6.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 6.8.1 www.ti.com Power Management and Supervisory Circuit Solutions Table 6-10 lists the power management and supervisory circuit solutions for 2833x/2823x devices. LDO selection depends on the total power consumed in the end application. Go to www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 VDDIO, VDD3VFL VDDA2, VDDAIO (3.3 V) VDD, VDD1A18, VDD2A18 (1.9 V/1.8 V) XCLKIN X1/X2 OSCCLK/16(A) XCLKOUT OSCCLK/8 User-Code Dependent tOSCST tw(RSL1) XRS Address/Data Valid.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Table 6-11.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Figure 6-8 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR = 0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 6.9.2 www.ti.com GPIO - Input Timing (A) GPIO Signal GPxQSELn = 1,0 (6 samples) 1 1 0 0 0 0 0 0 0 1 0 tw(SP) 0 0 1 1 1 1 1 1 1 1 1 Sampling Period determined by GPxCTRL[QUALPRD](B) tw(IQSW) (SYSCLKOUT cycle * 2 * QUALPRD) * 5(C)) Sampling Window SYSCLKOUT QUALPRD = 1 (SYSCLKOUT/2) (D) Output From Qualifier A. B. C. D.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com 6.9.3 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Sampling Window Width for Input Signals The following section summarizes the sampling window width for input signals for various input qualifier configurations. Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 6.9.4 www.ti.com Low-Power Mode Wakeup Timing Table 6-14 shows the timing requirements, Table 6-15 shows the switching characteristics, and Figure 612 shows the timing diagram for IDLE mode. Table 6-14.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Table 6-16. STANDBY Mode Timing Requirements tw(WAKE-INT) (1) Pulse duration, external wake-up signal TEST CONDITIONS MIN Without input qualification 3tc(OSCCLK) With input qualification (1) NOM MAX UNIT cycles (2 + QUALSTDBY) * tc(OSCCLK) QUALSTDBY is a 6-bit field in the LPMCR0 register. Table 6-17.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com (A) (C) (B) Device Status STANDBY (E) (D) (F) STANDBY Normal Execution Flushing Pipeline Wake-up Signal(G) tw(WAKE-INT) td(WAKE-STBY) X1/X2 or X1 or XCLKIN XCLKOUT td(IDLE−XCOL) A. B. C. D. E. F. G. IDLE instruction is executed to put the device into STANDBY mode. The PLL block responds to the STANDBY signal.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Table 6-18. HALT Mode Timing Requirements MIN tw(WAKE-GPIO) Pulse duration, GPIO wake-up signal tw(WAKE-XRS) Pulse duration, XRS wakeup signal (1) NOM MAX UNIT (1) cycles toscst + 8tc(OSCCLK) cycles toscst + 2tc(OSCCLK) See Table 6-11 for an explanation of toscst. Table 6-19.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 (A) www.ti.com (C) Device Status (D) HALT Flushing Pipeline (G) (E) (B) (F) HALT PLL Lock-up Time Wake-up Latency Normal Execution GPIOn(H) td(WAKE−HALT) tw(WAKE-GPIO) tp X1/X2 or XCLKIN Oscillator Start-up Time XCLKOUT td(IDLE−XCOL) A. B. C. D. E. F. G. H. IDLE instruction is executed to put the device into HALT mode. The PLL block responds to the HALT signal.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 6.10 Enhanced Control Peripherals 6.10.1 Enhanced Pulse Width Modulator (ePWM) Timing PWM refers to PWM outputs on ePWM1–6. Table 6-20 shows the PWM timing requirements and Table 621, switching characteristics. Table 6-20.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com 6.10.3 High-Resolution PWM Timing Table 6-23 shows the high-resolution PWM switching characteristics. Table 6-23. High-Resolution PWM Characteristics at SYSCLKOUT = (60–150 MHz) MIN Micro Edge Positioning (MEP) step size (1) (1) TYP MAX UNIT 150 310 ps Maximum MEP step size is based on worst-case process, maximum temperature and maximum voltage.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 6.10.5 Enhanced Quadrature Encoder Pulse (eQEP) Timing Table 6-26 shows the eQEP timing requirement and Table 6-27 shows the eQEP switching characteristics. Table 6-26.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com 6.10.6 ADC Start-of-Conversion Timing Table 6-28. External ADC Start-of-Conversion Switching Characteristics PARAMETER tw(ADCSOCL) MIN Pulse duration, ADCSOCxO low MAX 32tc(HCO ) UNIT cycles tw(ADCSOCL) ADCSOCAO or ADCSOCBO Figure 6-16. ADCSOCAO or ADCSOCBO Timing 6.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 6.12 I2C Electrical Specification and Timing Table 6-31.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Table 6-32. SPI Master Mode External Timing (Clock Phase = 0) (1) SPI WHEN (SPIBRR + 1) IS EVEN OR SPIBRR = 0 OR 2 NO. (2) (3) (4) (5) SPI WHEN (SPIBRR + 1) IS ODD AND SPIBRR > 3 UNIT MIN MAX MIN MAX 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) ns ns 1 tc(SPC)M Cycle time, SPICLK 2 tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 4 5 SPISIMO Master Out Data Is Valid 8 9 SPISOMI Master In Data Must Be Valid SPISTE(A) A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Table 6-33. SPI Master Mode External Timing (Clock Phase = 1) (1) SPI WHEN (SPIBRR + 1) IS EVEN OR SPIBRR = 0 OR 2 NO. (2) (3) (4) (5) SPI WHEN (SPIBRR + 1) IS ODD AND SPIBRR > 3 UNIT MIN MAX MIN MAX 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) ns ns 1 tc(SPC)M Cycle time, SPICLK 2 tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 6 7 Master Out Data Is Valid SPISIMO Data Valid 10 11 Master In Data Must Be Valid SPISOMI SPISTE(A) B. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com 6.13.2 SPI Slave Mode Timing Table 6-34 lists the slave mode external timing (clock phase = 0) and Table 6-35 (clock phase = 1). Figure 6-20 and Figure 6-21 show the timing waveforms. Table 6-34. SPI Slave Mode External Timing (Clock Phase = 0) (1) NO.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 12 SPICLK (clock polarity = 0) 13 14 SPICLK (clock polarity = 1) 15 16 SPISOMI SPISOMI Data Is Valid 19 20 SPISIMO SPISIMO Data Must Be Valid SPISTE(A) C. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) (minimum) before the valid SPI clock edge and remain low for at least 0.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Table 6-35. SPI Slave Mode External Timing (Clock Phase = 1) (1) NO. (2) (3) (4) MIN MAX 12 tc(SPC)S Cycle time, SPICLK 13 tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 0.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 6.14 External Interface (XINTF) Timing Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the Lead/Active/Trail wait states in the XTIMING registers. There is one XTIMING register for each XINTF zone.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com 6.14.2 Synchronous Mode (USEREADY = 1, READYMODE = 0) If the XREADY signal is sampled in the synchronous mode (USEREADY = 1, READYMODE = 0), then: 1 Lead: LR ≥ tc(XTIM) LW ≥ tc(XTIM) 2 Active: AR ≥ 2 × tc(XTIM) AW ≥ 2 × tc(XTIM) NOTE Restriction does not include external hardware wait states.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 6.14.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1) If the XREADY signal is sampled in the asynchronous mode (USEREADY = 1, READYMODE = 1), then: 1 LR ≥ tc(XTIM) Lead: LW ≥ tc(XTIM) 2 AR ≥ 2 × tc(XTIM) Active: AW ≥ 2 × tc(XTIM) 3 LR + AR ≥ 4 × tc(XTIM) Lead + Active: LW + AW ≥ 4 × tc(XTIM) NOTE Restrictions do not include external hardware wait states.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Unless otherwise specified, all XINTF timing is applicable for the clock configurations shown in Table 6-37. Table 6-37.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 6.14.4 XINTF Signal Alignment to XCLKOUT For each XINTF access, the number of lead, active, and trail cycles is based on the internal clock XTIMCLK. Strobes such as XRD, XWE0, XWE1, and zone chip-select (XZCS) change state in relationship to the rising edge of XTIMCLK.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com 6.14.5 External Interface Read Timing Table 6-38.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 (A)(B) Trail Active Lead (C) XCLKOUT = XTIMCLK XCLKOUT = 1/2 XTIMCLK td(XCOH-XZCSL) td(XCOHL-XZCSH) XZCS0, XZCS6, XZCS7 td(XCOH-XA) XA[0:19] td(XCOHL-XRDH) td(XCOHL-XRDL) XRD tsu(XD)XRD (D) XWE0, XWE1 XR/W ta(A) th(XD)XRD ta(XRD) XD[0:31], XD[0:15] XREADY A. B. C. D. E. DIN (E) All XINTF accesses (lead period) begin on the rising edge of XCLKOUT.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com 6.14.6 External Interface Write Timing Table 6-40.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 (A) (B) Active Lead (C) Trail XCLKOUT = XTIMCLK XCLKOUT = 1/2 XTIMCLK td(XCOHL-XZCSH) td(XCOH-XZCSL) XZCS0, XZCS6, XZCS7 td(XCOH-XA) XA[0:19] XRD td(XCOHL-XWEH) td(XCOHL-XWEL) (D) XWE0, XWE1 A. B. C. D. E.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com 6.14.7 External Interface Ready-on-Read Timing With One External Wait State Table 6-41.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 6.14.8 External Interface Ready-on-Write Timing With One External Wait State Table 6-45.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 6.14.9 www.ti.com XHOLD and XHOLDA Timing If the HOLD mode bit is set while XHOLD and XHOLDA are both low (external bus accesses granted), the XHOLDA signal is forced high (at the end of the current cycle) and the external interface is taken out of high-impedance mode. On a reset (XRS), the HOLD mode bit is set to 0.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Table 6-48.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Table 6-49.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 6.15 On-Chip Analog-to-Digital Converter Table 6-50. ADC Electrical Characteristics (over recommended operating conditions) (1) PARAMETER MIN TYP (2) MAX UNIT 25 MHz ±1.5 LSB ±2 LSB ±1 LSB –15 15 LSB –30 30 LSB –30 30 LSB DC SPECIFICATIONS (3) Resolution 12 ADC clock 0.001 Bits ACCURACY INL (Integral nonlinearity) 1-12.5 MHz ADC clock (6.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com 6.15.1 ADC Power-Up Control Bit Timing ADC Power Up Delay ADC Ready for Conversions PWDNBG PWDNREF td(BGR) PWDNADC td(PWD) Request for ADC Conversion Figure 6-31. ADC Power-Up Control Bit Timing Table 6-51. ADC Power-Up Delays PARAMETER (1) MIN td(BGR) Delay time for band gap reference to be stable.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Rs Source Signal ADCIN0 Ron 1 kΩ Switch Cp 10 pF ac Ch 1.64 pF 28x DSP Typical Values of the Input Circuit Components: Switch Resistance (Ron): Sampling Capacitor (Ch): Parasitic Capacitance (Cp): Source Resistance (Rs): 1 kΩ 1.64 pF 10 pF 50 Ω Figure 6-32. ADC Analog Input Impedance Model 6.15.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com 6.15.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0) In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax to Bx). The ADC can start conversions on event triggers from the ePWM, software trigger, or from an external ADCSOC signal.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 6.15.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels (A0/B0 to A7/B7). The ADC can start conversions on event triggers from the ePWM, software trigger, or from an external ADCSOC signal.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com 6.15.5 Detailed Descriptions Integral Nonlinearity Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. The point used as zero occurs one-half LSB before the first code transition. The full-scale point is defined as level one-half LSB beyond the last code transition.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 6.16 Multichannel Buffered Serial Port (McBSP) Timing 6.16.1 McBSP Transmit and Receive Timing Table 6-55. McBSP Timing Requirements (1) (2) NO.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Table 6-56. McBSP Switching Characteristics (1) NO.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 M1, M11 M2, M12 M13 M3, M12 CLKR M4 M4 M14 FSR (int) M15 M16 FSR (ext) M18 M17 DR (RDATDLY=00b) Bit (n−1) (n−2) (n−3) M17 (n−4) M18 DR (RDATDLY=01b) Bit (n−1) (n−2) (n−3) M17 M18 DR (RDATDLY=10b) Bit (n−1) (n−2) Figure 6-35.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com 6.16.2 McBSP as SPI Master or Slave Timing Table 6-57. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) NO.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Table 6-59. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) MASTER NO.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Table 6-61. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) NO.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Table 6-63. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) MASTER NO.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com 6.17 Flash Timing Table 6-65.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Table 6-70. Minimum Required Flash/OTP Wait-States at Different Frequencies SYSCLKOUT (MHz) SYSCLKOUT (ns) PAGE WAIT-STATE RANDOM WAITSTATE (1) OTP WAIT-STATE 150 6.67 5 5 8 120 8.33 4 4 7 100 10 3 3 5 75 13.33 2 2 4 50 20 1 1 2 30 33.33 1 1 1 25 40 1 1 1 15 66.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com 6.18 Migrating Between F2833x Devices and F2823x Devices The principal difference between these two devices is the absence of the floating-point unit (FPU) in the F2823x devices. This section describes how to build an application for each: • For F2833x devices: – Code Composer Studio 3.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com 7 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 L-to-M Revision History This data sheet revision history highlights the technical changes made to the SPRS439L device-specific data sheet to make it an SPRS439M revision. Scope: See table below.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 8 www.ti.com K-to-L Revision History This data sheet revision history highlights the technical changes made to the SPRS439K device-specific data sheet to make it an SPRS439L revision. Scope: See table below. LOCATION Table 3-16 Section 3.6.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 www.ti.com 9 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 Thermal and Mechanical Data Table 9-1, Table 9-2, Table 9-3, and Table 9-4 show the thermal data. See Section 6.4.3 for more information on thermal design considerations. The mechanical package diagrams that follow the tables reflect the most current released mechanical data available for the designated devices. Table 9-1.
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TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232 SPRS439M – JUNE 2007 – REVISED AUGUST 2012 www.ti.com Table 9-4. Thermal Model 176-Ball ZJZ Results AIR FLOW 188 PARAMETER 0 lfm 150 lfm 250 lfm θJA[°C/W] High k PCB 29.6 20.9 19.7 18 ΨJT[°C/W] 0.2 0.78 0.91 1.11 ΨJB 12.2 11.6 11.5 11.3 θJC 11.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 21-Jun-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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OCTOBER 1994 PGF (S-PQFP-G176) PLASTIC QUAD FLATPACK 132 89 88 133 0,27 0,17 0,08 M 0,50 0,13 NOM 176 45 1 44 Gage Plane 21,50 SQ 24,20 SQ 23,80 26,20 SQ 25,80 0,25 0,05 MIN 0°−ā 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040134 / B 03/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.