Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 (14x14) 16-Bit 40 MHz I/O number 41

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

D High-Performance Static CMOS Technology

− 25-ns Instruction Cycle Time (40 MHz)

− 40-MIPS Performance

− Low-Power 3.3-V Design

D Based on TMS320C2xx DSP CPU Core

− Code-Compatible With F243/F241/C242

− Instruction Set and Module Compatible

With F240

D Flash (LF) and ROM (LC) Device Options

− LF240xA: LF2407A, LF2406A,

LF2403A, LF2402A

− LC240xA: LC2406A, LC2404A,

LC2403A, LC2402A

D On-Chip Memory

− Up to 32K Words x 16 Bits of Flash

EEPROM (4 Sectors) or ROM

− Programmable “Code-Security” Feature

for the On-Chip Flash/ROM

− Up to 2.5K Words x 16 Bits of

Data/Program RAM

− 544 Words of Dual-Access RAM

− Up to 2K Words of Single-Access RAM

D Boot ROM (LF240xA Devices)

− SCI/SPI Bootloader

D Up to Two Event-Manager (EV) Modules

(EVA and EVB), Each Includes:

− Two 16-Bit General-Purpose Timers

− Eight 16-Bit Pulse-Width Modulation

(PWM) Channels Which Enable:

− Three-Phase Inverter Control

− Center- or Edge-Alignment of PWM

Channels

− Emergency PWM Channel Shutdown

With External PDPINTx

− Programmable Deadband (Deadtime)

Prevents Shoot-Through Faults

− Three Capture Units for Time-Stamping

of External Events

− Input Qualifier for Select Pins

− On-Chip Position Encoder Interface

Circuitry

− Synchronized A-to-D Conversion

− Designed for AC Induction, BLDC,

Switched Reluctance, and Stepper Motor

Control

− Applicable for Multiple Motor and/or

Converter Control

D External Memory Interface (LF2407A)

− 192K Words x 16 Bits of Total Memory:

64K Program, 64K Data, 64K I/O

D Watchdog (WD) Timer Module

D 10-Bit Analog-to-Digital Converter (ADC)

− 8 or 16 Multiplexed Input Channels

− 500-ns MIN Conversion Time

− Selectable Twin 8-State Sequencers

Triggered by Two Event Managers

D Controller Area Network (CAN) 2.0B Module

(LF2407A, 2406A, 2403A)

D Serial Communications Interface (SCI)

D 16-Bit Serial Peripheral Interface (SPI)

(LF2407A, 2406A, LC2404A, 2403A)

D Phase-Locked-Loop (PLL)-Based Clock

Generation

D Up to 40 Individually Programmable,

Multiplexed General-Purpose Input/Output

(GPIO) Pins

D Up to Five External Interrupts (Power Drive

Protection, Reset, Two Maskable Interrupts)

D Power Management:

− Three Power-Down Modes

− Ability to Power Down Each Peripheral

Independently

D Real-Time JTAG-Compliant Scan-Based

Emulation, IEEE Standard 1149.1

†

(JTAG)

D Development Tools Include:

− Texas Instruments (TI) ANSI C Compiler,

Assembler/Linker, and Code Composer

Studio Debugger

− Evaluation Modules

− Scan-Based Self-Emulation (XDS510)

− Broad Third-Party Digital Motor Control

Support

D Package Options

− 144-Pin LQFP PGE (LF2407A)

− 100-Pin LQFP PZ (2406A, LC2404A)

− 64-Pin TQFP PAG (LF2403A, LC2403A,

LC2402A)

− 64-Pin QFP PG (2402A)

D Extended Temperature Options (A and S)

− A: − 40°C to 85°C

− S: − 40°C to 125°C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Code Composer Studio and XDS510 are trademarks of Texas Instruments.

Other trademarks are the property of their respective owners.

†

IEEE Standard 1149.1−1990, IEEE Standard Test-Access Port; however, boundary scan is not supported in this device family.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Summary of content (134 pages)

PAGE 1
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 D High-Performance Static CMOS Technology D External Memory Interface (LF2407A) D D D D D D D − 25-ns Instruction Cycle Time (40 MHz) − 40-MIPS Performance − Low-Power 3.
PAGE 2
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 Table of Contents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 TMS320x240xA Device Summary . . . . . . . . . . . . . . . . . 5 Functional Block Diagram of the 2407A DSP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pinouts . . . . . . . . . . . . . . . . . .
PAGE 3
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 REVISION HISTORY PAGE HIGHLIGHTS 11 Added the VCCA pin to final note on Table 2 27 Modified LC2403A memory map (Figure 7) in location 8200 50 Added a sentence to the paragraph following Figure 12 59 Added 1/4 W to second column header in Table 10, Loop Filter Component Values With Damping Factor = 2.
PAGE 4
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 description The TMS320LF240xA and TMS320LC240xA devices, new members of the TMS320C24x generation of digital signal processor (DSP) controllers, are part of the TMS320C2000 platform of fixed-point DSPs.
PAGE 5
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 TMS320x240xA device summary Note that throughout this data sheet, 240xA is used as a generic name for the LF240xA/LC240xA generation of devices. Table 1.
PAGE 6
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 functional block diagram of the 2407A DSP controller PLLF PLLVCCA DARAM (B0) 256 Words XINT1/IOPA2 RS PLL Clock XTAL1/CLKIN CLKOUT/IOPE0 TMS2 BIO/IOPC1 MP/MC BOOT_EN/XF XTAL2 C2xx DSP Core DARAM (B1) 256 Words VDD (3.
PAGE 7
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 pinouts † ‡ ADCIN08 ADCIN00 ADCIN09 ADCIN01 ADCIN10 113 112 111 110 109 V CCA VREFHI VREFLO 114 115 116 BIO/ IOPC1 MP/MC V SSA 118 117 READY 119 ENA_144 121 BOOT_EN/XF ‡ XTAL1/CLKIN 122 120 XTAL2 123 130 124 IOPF6 D1 VDD 131 TCLKINB/ IOPF5 V SSO D2 132 125 RS 133 D0 D3 134 126 TCK 135 V S
PAGE 8
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 pinouts (continued) ADCIN11 ADCIN02 ADCIN12 ADCIN03 ADCIN13 ADCIN04 ADCIN05 ADCIN14 ADCIN06 ADCIN07 ADCIN15 V DDO V SSO EMU1/ OFF EMU0 CAP4/QEP3/ IOPE7 V DD V SS CAP1/QEP1/ IOPA3 CAP5/QEP4/ IOPF0 CAP2/QEP2/ IOPA4 V DDO V SSO CAP3/ IOPA5 CLKOUT/IOPE0 PZ PACKAGE† ( TOP VIEW ) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 5
PAGE 9
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 pinouts (continued) TMS2 SPICLK/IOPC4 SPISOMI/IOPC3 SPISIMO/IOPC2 SCIRXD/IOPA1 SCITXD/IOPA0 XINT2/ADCSOC/IOPD0 T2PWM/T2CMP/IOPB5 T1PWM/T1CMP/IOPB4 PLLV CCA PLLF PLLF2 PDPINTA VDDO VSSO TRST PAG PACKAGE†‡ (TOP VIEW) 48 47 46 45 44 4342 41 40 39 38 37 36 35 34 33 TCLKINA/IOPB7 PWM6/IOPB3 VSSO VDDO PWM5/IOPB2 PWM4/IOPB1 VSS VDD P
PAGE 10
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 pinouts (continued) TRST PDPINTA VDDO VSSO PLLF PLLF2 VSSO PWM6/ IOPB3 TCLKINA/ IOPB7 TMS2 IOPC4 IOPC3 IOPC2 SCIRXD/ IOPA1 SCITXD/ IOPA0 XINT2/ADCSOC/ IOPD0 T2PWM/T2CMP/ IOPB5 T1PWM/T1CMP/ IOPB4 PLLV CCA PG PACKAGE† (TOP VIEW) 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDDO PWM5/IOPB2 PWM4/IOPB1 VSS VDD PWM3/
PAGE 11
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 pin functions The TMS320LF2407A device is the superset of all the 240xA devices. All signals are available on the 2407A device. Table 2 lists the signals available in the 240xA generation of devices. Table 2.
PAGE 12
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 pin functions (continued) Table 2.
PAGE 13
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 pin functions (continued) Table 2.
PAGE 14
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 pin functions (continued) Table 2.
PAGE 15
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 pin functions (continued) Table 2.
PAGE 16
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 pin functions (continued) Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued) PIN NAME LF2407A (144-PGE) 2406A (100-PZ) LC2404A (100-PZ) 2403A, LC2402A (64-PAG) and 2402A (64-PG) DESCRIPTION EMULATION AND TEST (CONTINUED) TDI 139 96 96 30 JTAG test data input (TDI) with internal pullup.
PAGE 17
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 pin functions (continued) Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued) LF2407A (144-PGE) PIN NAME 2406A (100-PZ) LC2404A (100-PZ) 2403A, LC2402A (64-PAG) and 2402A (64-PG) DESCRIPTION ADDRESS, DATA, AND MEMORY CONTROL SIGNALS DS 87 Data space strobe.
PAGE 18
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 pin functions (continued) Table 2.
PAGE 19
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 pin functions (continued) Table 2.
PAGE 20
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 pin functions (continued) Table 2.
PAGE 21
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 memory maps Hex 0000 Hex 0000 Program Flash Sector 0 (4K) 005F 0060 007F 0080 00FF 0100 01FF 0200 Interrupt Vectors (0000−003Fh) Reserved † (0040−0043h) User code begins at 0044h 0FFF 1000 02FF 0300 03FF 0400 04FF 0500 07FF 0800 Flash Sector 1 (12K) 3FFF 4000 Flash Sector 2 (12K) 0FFF 1000 Data Hex 0000 Memory-Mapped
PAGE 22
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 memory maps (continued) Hex 0000 Hex 0000 Program Flash Sector 0 (4K) 005F 0060 007F 0080 00FF 0100 01FF 0200 User code begins at 0044h 0FFF 1000 02FF 0300 03FF 0400 04FF 0500 07FF 0800 Flash Sector 1 (12K) 3FFF 4000 Flash Sector 2 (12K) 6FFF 7000 Flash Sector 3 (4K) ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈ
PAGE 23
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 memory maps (continued) Hex Flash Sector 0 (4K) Interrupt Vectors (0000−003Fh) Reserved † (0040−0043h) 0000 0FFF 1000 3FFF 4000 Hex 0000 Program 005F 0060 007F 0080 00FF 0100 01FF 0200 User code begins at 0044h ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÉÉÉÉÉÉÉÉÉ ÈÈÈÈÈÈÈÈÈ ÉÉÉÉÉÉÉÉÉ ÉÉ
PAGE 24
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 memory maps (continued) Hex 0000 0FFF 1000 1FFF 2000 Flash Sector 0 (4K) Interrupt Vectors (0000−003Fh) Reserved † (0040−0043h) User code begins at 0044h ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÉÉÉÉÉÉÉÉÉÉ ÈÈÈÈÈÈÈÈÈÈ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈ
PAGE 25
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 memory maps (continued) Hex 0000 Program On-Chip ROM (32K) Interrupt Vectors (0000−003Fh) Reserved † (0040−0043h) User code begins at 0044h 7FBF 7FC0 ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ Reserved 7FFF 8000 87FF 8800 SARAM (2K) Int
PAGE 26
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 memory maps (continued) Hex 0000 Program On-Chip ROM (16K) Interrupt Vectors (0000−003Fh) Reserved † (0040−0043h) User code begins at 0044h 3FBF 3FC0 ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ
PAGE 27
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 memory maps (continued) Hex 0000 Program On-chip ROM (16K) Interrupt Vectors (0000−003Fh) Reserved † (0040−0043h) User code begins at 0044h 3FBF 3FCO 3FFF 4000 ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈ
PAGE 28
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 memory maps (continued) Hex 0000 17BF 17C0 17FF 1800 7FFF 8000 Program On-Chip ROM (6K) Interrupt Vectors (0000−003Fh) Reserved † (0040−0043h) User code begins at 0044h ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈÈ ÈÈÈÈ
PAGE 29
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 peripheral memory map of the 2407A/2406A Interrupt-Mask Register Hex 0000 0003 0004 Reserved 0005 Interrupt Flag Register 0006 0007 Reserved Emulation Registers and Reserved Hex 0000 005F 0060 007F 0080 00FF 0100 Memory-Mapped Registers and Reserved ÈÈÈÈÈÈÈÈÈ ÈÈÈÈÈÈÈÈÈ On-Chip DARAM B2 Illegal Reserved 01FF 0200 On-C
PAGE 30
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 device reset and interrupts The TMS320x240xA software-programmable interrupt structure supports flexible on-chip and external interrupt configurations to meet real-time interrupt-driven application requirements. The LF240xA recognizes three types of interrupt sources.
PAGE 31
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 device reset and interrupts (continued) PDPINTA PDPINTB XINT2 SPIINT RXINT TXINT CANMBINT CANERINT CMP1INT CMP2INT CMP3INT CMP4INT CMP5INT CMP6INT T1PINT T1CINT T1UFINT T1OFINT T3PINT T3CINT T3UFINT T3OFINT T2PINT T2CINT T2UFINT T2OFINT T4PINT T4CINT T4UFINT T4OFINT IMR IFR Level 1 IRQ GEN INT1 INT2 Level 2 IRQ GEN CPU INT
PAGE 32
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 interrupt request structure Table 3.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 interrupt request structure (continued) Table 3. LF240xA/LC240xA Interrupt Source Priority and Vectors (Continued) INTERRUPT NAME OVERALL PRIORITY CPU INTERRUPT AND VECTOR ADDRESS BIT POSITION IN PIRQRx AND PIACKRx PERIPHERAL INTERRUPT VECTOR (PIV) MASKABLE? SOURCE PERIPHERAL MODULE DESCRIPTION T2PINT 28 1.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 DSP CPU core The TMS320x240xA devices use an advanced Harvard-type architecture that maximizes processing power by maintaining two separate memory bus structures — program and data — for full-speed execution. This multiple bus structure allows data and instructions to be read simultaneously.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 functional block diagram of the 2407A DSP CPU Program Bus IS DS PS PC PAR Program Bus Control NPAR 16 MSTACK MUX RD WE RS MP/MC XINT[1−2] MUX XTAL1 CLKOUT XTAL2 Data Bus R/W STRB READY XF Stack 8 × 16 2 FLASH EEPROM/ ROM MUX A15−A0 16 Program Control (PCTRL) 16 16 16 16 16 MUX D15−D0 16 16 Data Bus 16 Da
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 240xA legend for the internal hardware Table 4. Legend for the 240xA DSP CPU Internal Hardware SYMBOL NAME DESCRIPTION ACC Accumulator 32-bit register that stores the results and provides input for subsequent CALU operations.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 240xA legend for the internal hardware (continued) Table 4. Legend for the 240xA DSP CPU Internal Hardware (Continued) SYMBOL NAME DESCRIPTION PREG Product Register 32-bit register holds results of 16 × 16 multiply PSCALE Product-Scaling Shifter 0-, 1-, or 4-bit left shift, or 6-bit right shift of multiplier product.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 status and control registers (continued) Table 5. Status Register Field Definitions (Continued) FIELD FUNCTION DP Data memory page pointer. The 9-bit DP register is concatenated with the 7 LSBs of an instruction word to form a direct memory address of 16 bits. DP can be modified by the LST and LDP instructions.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 multiplier The TMS320x240xA devices use a 16 x 16-bit hardware multiplier that is capable of computing a signed or an unsigned 32-bit product in a single machine cycle. All multiply instructions, except the MPYU (multiply unsigned) instruction, perform a signed multiply operation.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 multiplier (continued) The MPYU instruction performs an unsigned multiplication, which greatly facilitates extended-precision arithmetic operations. The unsigned contents of TREG are multiplied by the unsigned contents of the addressed data memory location, with the result placed in PREG.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 central arithmetic logic unit (continued) The CALU also has an associated carry bit that is set or reset depending on various operations within the device. The carry bit allows more efficient computation of extended-precision products and additions or subtractions. It is also useful in overflow management.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 internal memory The TMS320x240xA devices are configured with the following memory modules: D D D D D Dual-access random-access memory (DARAM) Single-access random-access memory (SARAM) Flash ROM Boot ROM dual-access RAM (DARAM) There are 544 words × 16 bits of DARAM on the 240xA devices.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 boot ROM (LF240xA only) Boot ROM is a 256-word ROM memory-mapped in program space 0000−00FF. This ROM will be enabled if the BOOT_EN pin is low during reset. The BOOT_EN bit (bit 3 of the SCSR2 register) will be set to 0 if the BOOT_EN pin is low at reset. Boot ROM can also be enabled by writing 0 to the SCSR2.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 PERIPHERALS The integrated peripherals of the TMS320x240xA are described in the following subsections: D D D D D D D D D Two event-manager modules (EVA, EVB) Enhanced analog-to-digital converter (ADC) module Controller area network (CAN) module Serial communications interface (SCI) module Serial peripheral interface (SPI) modul
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 event manager modules (EVA, EVB) (continued) 240xA DSP Core Data Bus 16 ADDR Bus Reset INT2,3,4 Clock 16 16 16 3 EV Control Registers and Control Logic ADC Start of Conversion Output Logic GP Timer 1 Compare T1PWM/ T1CMP TDIRA† 16 GP Timer 1 16 16 T1CON[4,5] Full-Compare Units TCLKINA Prescaler 3 SVPWM State Ma
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 general-purpose (GP) timers There are two GP timers.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 PWM characteristics Characteristics of the PWMs are as follows: D D D D D D D D D 16-bit registers Programmable deadband for the PWM output pairs, from 0 to 12 µs Minimum deadband width of 25 ns Change of the PWM carrier frequency for PWM frequency wobbling as needed Change of the PWM pulse widths within and after each PWM per
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 input qualifier circuitry An input-qualifier circuitry qualifies the input signal to the CAP1−6, QEP1−4, XINT1/2, ADCSOC and PDPINTA/B pins in the 240xA devices. (The I/O functions of these pins do not use the input-qualifier circuitry).
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 enhanced analog-to-digital converter (ADC) module (continued) The ADC module in the 240xA has been enhanced to provide flexible interface to event managers A and B. The ADC interface is built around a fast, 10-bit ADC module with a total minimum conversion time of 375 ns (S/H + conversion).
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 controller area network (CAN) module The CAN module is a full-CAN controller designed as a 16-bit peripheral module and supports the following features: D CAN specification 2.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 controller area network (CAN) module (continued) The mailboxes are situated in one 48-word x 16-bit RAM. It can be written to or read by the CPU or the CAN. The CAN write or read access, as well as the CPU read access, needs one clock cycle. The CPU write access needs two clock cycles.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 serial communications interface (SCI) module The 240xA devices include a serial communications interface (SCI) module. The SCI module supports digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 serial communications interface (SCI) module (continued) TXWAKE Frame Format and Mode SCICTL1.3 SCITXBUF.7−0 Transmitter-Data Buffer Register Parity Even/Odd Enable SCICCR.6 SCICCR.5 SCI TX Interrupt TXRDY TX INT ENA SCICTL2.7 TX EMPTY 8 TXINT SCICTL2.0 External Connections SCICTL2.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 serial peripheral interface (SPI) module Some 240xA devices include the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 serial peripheral interface (SPI) module (continued) Figure 15 is a block diagram of the SPI in slave mode. SPIRXBUF.15 −0 Receiver Overrun Flag SPIRXBUF Buffer Register SPISTS.7 SPITXBUF Buffer Register SPI INT FLAG SPI Priority 0 Level 1 INT 1 Level 5 INT SPIPRI.6 To CPU SPICTL.4 SPITXBUF.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 SPI slave mode operation in LF2403A The LF2403A device does not have the SPISTE/IOPC5 pin. (This function is available as an internal signal only.) The following must be done to put the LF2403A SPI in slave mode: 1. Configure SPISTE/IOPC5 signal for GPIO mode by clearing the MCRB.5 bit. 2.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 PLL-based clock module (continued) XTAL1/CLKIN Cb1 RESONATOR/ CRYSTAL XTAL2 Fin Cb2 PLL CLKOUT PLLF R1 C2 XTAL OSC 3-bit PLL Select (SCSR1.[11:9]) C1 PLLF2 Figure 16. PLL Clock Module Block Diagram Table 9.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 external reference oscillator clock option (continued) XTAL1/CLKIN XTAL2 Crystal XTAL1/CLKIN XTAL2 External Clock Signal (Toggling 0 −3.3 V) NC Cb2 (see Note A) Cb1 (see Note A) (a) (b) NOTE A: TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the DSP chip.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 clock domains All 240xA-based devices have two clock domains: 1. CPU clock domain − consists of the clock for most of the CPU logic 2. System clock domain − consists of the peripheral clock (which is derived from CLKOUT of the CPU) and the clock for the interrupt logic in the CPU.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 digital I/O and shared pin functions (continued) D Output Control Registers — used to control the multiplexer selection that chooses between the primary function of a pin or the general-purpose I/O function. D Data and Control Registers — used to control the data and data direction of bidirectional I/O pins.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 description of shared I/O pins (continued) Table 12. Shared Pin Configurations† (MCRx.n = 1) Primary Function (MCRX.N = 0) I/O MUX CONTROL REGISTER (name.bit #) SCITXD IOPA0 MCRA.0 0 SCIRXD IOPA1 MCRA.1 XINT1 IOPA2 MCRA.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 description of shared I/O pins (continued) Table 12. Shared Pin Configurations† (Continued) PIN FUNCTION SELECTED (MCRx.n = 1) Primary Function (MCRX.N = 0) I/O MUX CONTROL REGISTER (name.bit #) MUX CONTROL VALUE AT RESET (MCRx.n) I/O PORT DATA AND DIRECTION‡ REGISTER DATA BIT NO.§ DIR BIT NO.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 external memory interface (LF2407A) The TMS320LF2407A can address up to 64K × 16 words of memory (or registers) in each of the program, data, and I / O spaces. On-chip memory, when enabled, occupies some of this off-chip range.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 generating wait states with the READY signal When the READY signal is low, the LF2407A waits one CLKOUT cycle and then checks READY again. The LF2407A does not continue executing until the READY signal is driven high; therefore, if the READY signal is not used, it should be pulled high.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 watchdog (WD) timer module (continued) CLKOUT ÷ 512 WDCLK System Reset 6-Bit FreeRunning Counter 3-bit Prescaler PLL CLKIN /64 /32 On-Chip Oscillator or External Clock /16 /8 /4 /2 CLR 000 001 010 011 WDPS WDCR.2 −0 2 1 0 WDCR.6 WDDIS 100 101 110 111 WDFLAG WDCR.7 WDCNTR.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 watchdog (WD) timer module (continued) Table 14.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 development support (continued) Table 16.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 device and development support tool nomenclature (continued) Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 documentation support Extensive documentation supports all of the TMS320 DSP family generations of devices from product announcement through applications development.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 LF240xA AND LC240xA ELECTRICAL SPECIFICATIONS DATA absolute maximum ratings over operating free-air temperature ranges (unless otherwise noted)† Supply voltage range, VDD, PLLVCCA, VDDO, and VCCA (see Note 1) . . . . . . . . . . . . . . . . . . . − 0.3 V to 4.6 V VCCP range . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 electrical characteristics over recommended operating free-air temperature ranges (unless otherwise noted) PARAMETER † TEST CONDITIONS VDD = 3.0 V, IOH = IOHMAX MIN TYP 2.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 current consumption by power-supply pins over recommended operating free-air temperature ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LF2407A) PARAMETER IDD† Operational Current ICCA ADC module current IDD † ‡ † Operational Current ICCA ADC module current IDD† Operational Current ICCA ADC module current M
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 current consumption by power-supply pins over recommended operating free-air temperature ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LF2402A) PARAMETER IDD† Operational Current ICCA ADC module current IDD † ‡ † Operational Current ICCA ADC module current IDD† Operational Current ICCA ADC module current
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 current consumption by power-supply pins over recommended operating free-air temperature ranges during low-power modes at 40-MHz CLOCKOUT (TMS320LC2403A) PARAMETER IDD† Operational Current ICCA ADC module current IDD † Operational Current ICCA ADC module current IDD† Operational Current MODE † ‡ MIN TYP MAX UNIT
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 current consumption graphs 100 90 80 Current (mA) I DD 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 40 45 CLKOUT Frequency (MHz) Figure 21.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 6 inches or less VDDO VDDIO 13 EMU0 14 EMU1 2 TRST 1 TMS 3 TDI 7 TDO 11 TCK 9 DSP PD EMU0 EMU1 TRST GND TMS GND TDI GND TDO GND TCK GND 5 4 6 8 10 12 TCK_RET JTAG Header Figure 23.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 PARAMETER MEASUREMENT INFORMATION IOL Tester Pin Electronics Output Under Test 50 Ω VLOAD CT IOH Where: IOL IOH VLOAD CT = = = = 2 mA (all outputs) 300 µA (all outputs) 1.5 V 50-pF typical load-circuit capacitance Figure 24. Test Load Circuit signal transition levels The data in this section is shown for the 3.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 Input transition times are specified as follows: D For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is 90% of the total voltage range and lower and the level at which the input is said to be low is 10% of the total voltage range and lower.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 external reference crystal/clock with PLL circuit enabled timing parameters with the PLL circuit enabled PARAMETER Input clock frequency† fx † MIN MAX Resonator 4 13 Crystal 4 20 CLKIN 4 20 UNIT MHz Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz minimum.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 RS timing timing requirements for a reset [H = 0.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 RS timing (continued) tp tw(RSL2) td(EX) RS CLKIN XTAL1† BOOT_EN /XF BOOT_EN XF CLKOUT I/Os Hi-Z Code-Dependent Address/ Data/ Control † Address/Data/Control Valid XTAL1 refers to internal oscillator clock if on-chip oscillator is used. Figure 29.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 RS timing (continued) switching characteristics over recommended operating conditions for a reset [H = 0.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 low-power mode timing switching characteristics over recommended operating conditions [H = 0.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 LPM2 wakeup timing switching characteristics over recommended operating conditions (see Figure 34) PARAMETER † td(PDP-PWM)HZ Delay time, PDPINTA low to PWM high-impedance state td(INT) Delay time, INT low/high to interrupt-vector fetch MIN MAX UNIT if bit 6 of SCSR2 = 0 (6 + 1)tc(CO) + 12† ns if bit 6 of SCSR2 = 1 12
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 XF, BIO, and MP/MC timing switching characteristics over recommended operating conditions (see Figure 35) PARAMETER td(XF) Delay time, CLKOUT high to XF high/low MIN MAX −3 7 MIN MAX UNIT ns timing requirements (see Figure 35) tsu(BIO)CO Setup time, BIO or MP/MC low before CLKOUT low th(BIO)CO Hold time, BIO or MP/MC
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 TIMING EVENT MANAGER INTERFACE PWM timing PWM refers to all PWM outputs on EVA and EVB. switching characteristics over recommended operating conditions for PWM timing [H = 0.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 capture and QEP timing CAP refers to all QEP and capture input pins. timing requirements (see Figure 38) MIN tw(CAP)† † Pulse duration duration, CAPx input low/high if bit 6 of SCSR2 = 0 6tc(CO) if bit 6 of SCSR2 = 1 12tc(CO) This is different from 240x devices. CLKOUT tw(CAP) CAPx Figure 38.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 interrupt timing INT refers to XINT1 and XINT2. PDP refers to PDPINTx.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 general-purpose input/output timing switching characteristics over recommended operating conditions (see Figure 40) PARAMETER MIN MAX UNIT td(GPO)CO Dela time Delay time, CLKOUT lo low to GPIO low/high lo /high All GPIOs 9 ns tr(GPO) Rise time, GPIO switching low to high All GPIOs 8 ns tf(GPO) Fall time, GPIO swit
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SPI MASTER MODE TIMING PARAMETERS SPI master mode timing information is listed in the following tables. SPI master mode external timing parameters (clock phase = 0)†‡ (see Figure 42) SPI WHEN (SPIBRR + 1) IS EVEN OR SPIBRR = 0 OR 2 NO. 1 MIN MAX 4tc(CO) 128tc(CO) 5tc(CO) 127tc(CO) Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M −10 0.5tc(SPC)M 0.5tc(SPC)M −0.5tc(CO) −10 0.5tc(SPC)M −0.5tc(CO) tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M −10 0.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 PARAMETER MEASUREMENT INFORMATION 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 4 5 SPISIMO Master Out Data Is Valid 8 9 SPISOMI Master In Data Must Be Valid SPISTE† † The SPISTE signal is active before the SPI communication stream starts; the SPISTE signal remains active until the SPI communication stream
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SPI master mode external timing parameters (clock phase = 1)†‡ (see Figure 43) SPI WHEN (SPIBRR + 1) IS EVEN OR SPIBRR = 0 OR 2 NO. 1 MAX MIN MAX 4tc(CO) 128tc(CO) 5tc(CO) 127tc(CO) Cycle time, SPICLK tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M −10 0.5tc(SPC)M 0.5tc(SPC)M −0.5tc (CO)−10 0.5tc(SPC)M − 0.5tc(CO) tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M −10 0.5tc(SPC)M 0.5tc(SPC)M −0.5tc (CO)−10 0.5tc(SPC)M −0.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 PARAMETER MEASUREMENT INFORMATION 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 6 7 SPISIMO Data Valid Master Out Data Is Valid 10 11 Master In Data Must Be Valid SPISOMI SPISTE† † The SPISTE signal is active before the SPI communication stream starts; the SPISTE signal remains active until the SPI communicat
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 SPI slave mode timing parameters Slave mode timing information is listed in the following tables. SPI slave mode external timing parameters (clock phase = 0)†‡ (see Figure 44) NO. 12 13§ 14§ 15§ MIN tc(SPC)S Cycle time, SPICLK tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S −10 0.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 SPI slave mode external timing parameters (continued) 12 SPICLK (clock polarity = 0) 13 14 SPICLK (clock polarity = 1) 15 16 SPISOMI SPISOMI Data Is Valid 19 20 SPISIMO SPISIMO Data Must Be Valid SPISTE† † The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active until
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 SPI slave mode timing parameters (continued) SPI slave mode external timing parameters (clock phase = 1)†‡ (see Figure 45) NO. 12 13§ 14§ 17§ MIN Cycle time, SPICLK tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S −10 0.5tc(SPC)S tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 SPI slave mode timing parameters (continued) 12 SPICLK (clock polarity = 0) 13 14 SPICLK (clock polarity = 1) 17 18 SPISOMI SPISOMI Data Is Valid Data Valid 21 22 SPISIMO SPISIMO Data Must Be Valid SPISTE† † The SPISTE signal must be active before the SPI communication stream starts; the SPISTE signal must remain active un
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 external memory interface read timing switching characteristics over recommended operating conditions for an external memory interface read at 40 MHz [H = 0.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 external memory interface read timing (continued) CLKOUT td(COL−CNTL) td(COL−CNTH) PS, DS, IS td(COL−A)RD td(COL−A)RD th(A)COL th(A)COL A[0:15] td(COH−RDL) td(COL−RDH) ta(A) td(COH−RDL) td(COL−RDH) th(A)RD RD tsu(A)RD th(AIV−D) ta(A) tsu(D)RD td(WRN) ta(RD) th(D)RD tsu(D)RD th(D)RD W/R R/W D[0:15] td(COL−SL) td(COL−S
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 external memory interface write timing switching characteristics over recommended operating conditions for an external memory interface write at 40 MHz [H = 0.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 external memory interface write timing (continued) CLKOUT td(COH−CNTL) td(COH−CNTH) td(COH−CNTL) PS, DS, IS td(COH−A)W th(A)COLW A[0:15] td(COH−RWL) td(COH−RWH) tsu(A)W R/W td(WRN) W/R td(COL−WH) td(COL−WL) td(COL−WL) td(COL−WH) WE tdis(W-D) ten(D)COL ten(D)COL tsu(D)W th(D)W tsu(D)W th(D)W D[0:15] td(COL−SL) td(
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 external memory interface ready-on-read timing switching characteristics over recommended operating conditions for an external memory interface ready-on-read (see Figure 48) PARAMETER td(COL-A)RD MIN MAX 8 Delay time, CLKOUT low to address valid UNIT ns timing requirements for an external memory interface ready-on-read (see
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 external memory interface ready-on-read timing (continued) timing requirements for an external memory interface ready-on-read with one software wait state and one external wait state (see Figure 49) MIN MAX UNIT th(RDY)COH Hold time, READY after CLKOUT high H − 2.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 external memory interface ready-on-write timing switching characteristics over recommended operating conditions for an external memory interface ready-on-write (see Figure 50) PARAMETER td(COH-A)W MIN MAX 10 Delay time, CLKOUT high to address valid UNIT ns timing requirements for an external memory interface ready-on-write [
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 external memory interface ready-on-write timing (continued) timing requirements for an external memory interface ready-on-write with one software wait state and one external wait state (see Figure 51) MIN MAX UNIT th(RDY)COH Hold time, READY after CLKOUT high H − 2.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 10-bit analog-to-digital converter (ADC) The 10-bit ADC has a separate power bus for its analog circuitry. These pins are referred to as VCCA and VSSA.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 10-bit analog-to-digital converter (ADC) (continued) operating characteristics over recommended operating condition ranges† PARAMETER DESCRIPTION MIN VCCA = 3.3 V ICCA Analog supply current IADREFHI VREFHI input current IADCIN Analog input leakage VCCA = VREFHI = 3.3 V MAX 10 22 mA 1 µA 1.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 10-bit analog-to-digital converter (ADC) (continued) internal ADC module timing† (see Figure 52) MIN MAX UNIT tc(AD) C l time, Cycle ti ADC prescaled al d clock l k 33 33.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 Flash parameters @40 MHz CLOCKOUT† PARAMETER MIN TYP Time/Word (16-bit) Clear/Programming time‡ Erase time‡ ICCP (VCCP pin current) † ‡ MAX UNIT 30 µs Time/4K Sector 130 ms Time/12K Sector 400 ms Time/4K Sector 350 ms Time/12K Sector 1 Indicates the typical/maximum current consumption during the Clear-Erase-Pr
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 migrating from 240x devices to 240xA devices This section highlights the new features/migration issues of the 240xA devices (as compared to the 240x family) and describes the impact these features/issues have on user applications.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 migrating from LF240x devices to LC240xA devices When migrating from an “unsecured” Flash device (LF240x) to a “secured” ROM device (LC240xA), two migration paths have to be taken into consideration: D Migrating from a 240x device to a 240xA device (see the Migrating From 240x Devices to 240xA Devices section) D Migrating from
PAGE 113
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 peripheral register description Table 19 is a collection of all the programmable registers of the LF240xA/LC240xA and is provided as a quick reference. Table 19.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 peripheral register descriptions (continued) Table 19.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 peripheral register descriptions (continued) Table 19.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 peripheral register descriptions (continued) Table 19.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 peripheral register descriptions (continued) Table 19.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 peripheral register descriptions (continued) Table 19.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 peripheral register descriptions (continued) Table 19.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 peripheral register descriptions (continued) Table 19.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 peripheral register descriptions (continued) Table 19.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 peripheral register descriptions (continued) Table 19.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 peripheral register descriptions (continued) Table 19.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 peripheral register descriptions (continued) Table 19.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 peripheral register descriptions (continued) Table 19.
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 MECHANICAL DATA Table 20 through Table 23 provide the typical thermal resistance characteristics for each mechanical package. Table 20. Typical Thermal Resistance Characteristics for the PAG Package PARAMETER DESCRIPTION °C / W ΘJA Junction-to-ambient 42 ΘJC Junction-to-case 7 Ψjt Junction-to-top of package 0.
PAGE 127
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 MECHANICAL DATA (CONTINUED) The following mechanical package diagram(s) reflect the most current released mechanical data available for the designated device(s).
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 4-Apr-2013 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
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MECHANICAL DATA MQFP008 – JULY 1998 PG (R-PQFP-G64) PLASTIC QUAD FLATPACK 0,45 0,25 1,00 51 0,20 M 33 52 32 12,00 TYP 64 14,20 13,80 18,00 17,20 20 1 19 0,15 NOM 18,00 TYP 20,20 19,80 24,00 23,20 Gage Plane 0,25 0,10 MIN 2,70 TYP 0°– 10° 1,10 0,70 Seating Plane 3,10 MAX 0,10 4040101 / B 03/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 75 0,08 M 51 76 50 100 26 1 0,13 NOM 25 12,00 TYP Gage Plane 14,20 SQ 13,80 16,20 SQ 15,80 0,05 MIN 1,45 1,35 0,25 0°– 7° 0,75 0,45 Seating Plane 0,08 1,60 MAX 4040149 /B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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MECHANICAL DATA MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996 PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK 108 73 109 72 0,27 0,17 0,08 M 0,50 144 0,13 NOM 37 1 36 Gage Plane 17,50 TYP 20,20 SQ 19,80 22,20 SQ 21,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040147 / C 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.