Serial RapidIO (SRIO) User's Guide

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5.25 Error, Reset, and Special Event Interrupt Condition Clear Register
SRIO Registers
(ERR_RST_EVNT_ICCR)
Each bit in this register is used to clear the corresponding status bit in ERR_RST_EVNT_ICSR. The field
of ERR_RST_EVNT_ICCR are shown in Figure 86 and described in Table 76 . For additional programming
information, see Section 4.3.4 .
Figure 86. Error, Reset, and Special Event Interrupt Condition Clear Register
(ERR_RST_EVNT_ICCR) - Address Offset 0278h
31 17 16
Reserved ICC16
R-0 W-0
15 12 11 10 9 8 7 3 2 1 0
Reserved ICC11 ICC10 ICC9 ICC8 Reserved ICC2 ICC1 ICC0
R-0 W-0 W-0 W-0 W-0 R-0 W-0 W-0 W-0
LEGEND: R = Read only; W = Write only; - n = Value after reset
Table 76. Error, Reset, and Special Event Interrupt Condition Clear Register
(ERR_RST_EVNT_ICCR) Field Descriptions
Bit Field Value Description
31–17 Reserved 0 These read-only bits return 0s when read.
16 ICC16 0 No effect
1 Clear bit 16 of ERR_RST_EVNT_ICSR.
15–12 Reserved 0 These read-only bits return 0s when read.
11–8 ICC x 0 No effect
(x = 11 to 8)
1 Clear bit x of ERR_RST_EVNT_ICSR.
7–3 Reserved 0 These read-only bits return 0s when read.
2–0 ICC y 0 No effect
(y = 2 to 0)
1 Clear bit y of ERR_RST_EVNT_ICSR.
SPRUE13A – September 2006 Serial RapidIO (SRIO) 143
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