Serial RapidIO (SRIO) User's Guide

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2.3.9 Endianness
SRIO Functional Description
Table 25. Fields Within Each Flow Mask
Bit Field Value Description
15 FL15 0 TX source does not support Flow 15 from table entry
1 TX source supports Flow 15 from table entry
14 FL14 0 TX source does not support Flow 14 from table entry
1 TX source supports Flow 14 from table entry
13 FL13 0 TX source does not support Flow 13 from table entry
1 TX source supports Flow 13 from table entry
12 FL12 0 TX source does not support Flow 12 from table entry
1 TX source supports Flow 12 from table entry
11 FL11 0 TX source does not support Flow 11 from table entry
1 TX source supports Flow 11 from table entry
10 FL10 0 TX source does not support Flow 10 from table entry
1 TX source supports Flow 10 from table entry
9 FL9 0 TX source does not support Flow 9 from table entry
1 TX source supports Flow 9 from table entry
8 FL8 0 TX source does not support Flow 8 from table entry
1 TX source supports Flow 8 from table entry
7 FL7 0 TX source does not support Flow 7 from table entry
1 TX source supports Flow 7 from table entry
6 FL6 0 TX source does not support Flow 6 from table entry
1 TX source supports Flow 6 from table entry
5 FL5 0 TX source does not support Flow 5 from table entry
1 TX source supports Flow 5 from table entry
4 FL4 0 TX source does not support Flow 4 from table entry
1 TX source supports Flow 4 from table entry
3 FL3 0 TX source does not support Flow 3 from table entry
1 TX source supports Flow 3 from table entry
2 FL2 0 TX source does not support Flow 2 from table entry
1 TX source supports Flow 2 from table entry
1 FL1 0 TX source does not support Flow 1 from table entry
1 TX source supports Flow 1 from table entry
0 FL0 0 TX source does not support Flow 0 from table entry
1 TX source supports Flow 0 from table entry
RapidIO is based on Big Endian. This is discussed in detail in Section 2.4 of the RapidIO Interconnect
Specification. Essentially, Big Endian specifies the address ordering as the most significant bit/byte first.
For example, in the 29-bit address field of a RapidIO packet (shown in Figure 6 ) the left-most bit that is
transmitted first in the serial bit stream is the MSB of the address. Likewise, the data payload of the packet
is double-word aligned Big Endian, which means the MSB is transmitted first. Bit 0 of all the
RapidIO-defined MMR registers is the MSB.
All Endian-specific conversion is handled within the peripheral. For double-word aligned payloads, the
data should be written contiguously into memory beginning at the specified address. Any unaligned
payloads will be padded and properly aligned within the 8-byte boundary. In this case, WDPTR, RDSIZE,
and WRSIZE RapidIO header fields indicate the byte position of the data within the double-word
boundary. An example of an unaligned transfer is shown in Section 2.4 of the RapidIO Interconnect
Specification.
68 Serial RapidIO (SRIO) SPRUE13A – September 2006
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