Network Router User Manual

TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL 1992–REVISED MARCH 1993
POST OFFICE BOX 1443 • HOUSTON, TEXAS
77251–1443
38
PARAMETER MEASUREMENT INFORMATION
memory bus timing: clocks, MRAS
, MCAS, and MAL to ADDRESS
t
M
is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum)
NO. PARAMETER MIN MAX UNIT
15
Setup time of row address on MADL0–MADL7, MAXPH, and MAXPL before MRAS no longer
high
1.5t
M
– 11.5 ns
16 Hold time of row address on MADL0–MADL7, MAXPH, and MAXPL after MRAS no longer high t
M
–6.5 ns
17 Delay time from MRAS no longer high to MRAS no longer high in the next memory cycle 8t
M
ns
18 Pulse duration of MRAS low 4.5t
M
–9 ns
19 Pulse duration of MRAS high 3.5t
M
–9 ns
20
Setup time of column address (MADL0–MADL7, MAXPH, and MAXPL) and status
(MADH0–MADH7) before MCAS
no longer high
0.5t
M
–9 ns
21
Hold time of column address (MADL0–MADL7, MAXPH, and MAXPL) and status
(MADH0–MADH7) after MCAS
low
t
M
–9 ns
22
Hold time of column address (MADL0–MADL7, MAXPH, and MAXPL) and status
(MADH0–MADH7) after MRAS
no longer high
2.5t
M
–6.5 ns
23 Pulse duration of MCAS low 3t
M
–9 ns
24 Pulse duration of MCAS high, refresh cycle follows read or write cycle 2t
M
–9 ns
25 Hold time of row address on MAXL0–MAXL7, MAXPH, and MAXPL after MAL low 1.5t
M
–9 ns
26 Setup time of row address on MAXL0–MAXL7, MAXPH, and MAXPL before MAL no longer high t
M
–9 ns
27 Pulse duration of MAL high t
M
–9 ns
28 Setup time of address/enable on MAX0, MAX2, and MROMEN before MAL no longer high t
M
–9 ns
29 Hold time of address/enable of MAX0, MAX2, and MROMEN after MAL low 1.5t
M
–9 ns
30 Setup time of address on MADH0–MADH7 before MAL no longer high t
M
–9 ns
31 Hold time of address on MADH0–MADH7 after MAL low 1.5t
M
–9 ns