Network Card User Manual

Contents
ix Contents
A.1.13 PCI Memory Base Address Register (@ 14h) A-8. . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.14 PCI BIOS ROM Base Address Register (@ 30h) A-8. . . . . . . . . . . . . . . . . . . . . . . .
A.1.15 PCI NVRAM Register (@ 34h) A-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.16 PCI Interrupt Line Register (@ 3Ch) A-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.17 PCI Interrupt Pin Register (@ 3Dh) A-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.18 PCI Min_Gnt (@ 3Eh) and Max_Lat (@ 3Fh) Registers A-10. . . . . . . . . . . . . . . . . .
A.1.19 PCI Reset Control Register (@ 40h) A-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.1.20 CardBus CIS Pointer (@ 28h) A-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.2 Adapter Host Registers A-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.2.1 Host Command Register–HOST_CMD @ Base_Address + 0 (Host) A-12. . . . . .
A.2.2 Channel Parameter Register–CH_PARM @ Base_Address + 4 (Host) A-17. . . .
A.2.3 Host Interrupt Register–HOST_INT @ Base_Address + 10 (Host) A-18. . . . . . . .
A.2.4 DIO Address Register–DIO_ADR @ Base_Address + 8 (Host) A-19. . . . . . . . . . .
RAM Addressing A-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.2.5 DIO Data Register–DIO_DATA @ Base_Address + 12 (Host) A-20. . . . . . . . . . . .
A.3 Adapter Internal Registers A-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.3.1 Network Command Register–NetCmd @ 0x00 (DIO) A-23. . . . . . . . . . . . . . . . . . .
A.3.2 Network Serial I/O Register–NetSio @ 0x00 (DIO) A-24. . . . . . . . . . . . . . . . . . . . .
A.3.3 Network Status Register–NetSts @ 0x00 (DIO) A-25. . . . . . . . . . . . . . . . . . . . . . . .
A.3.4 Network Status Mask Register–NetMask @ 0x00 (DIO) A-26. . . . . . . . . . . . . . . . .
A.3.5 Network Configuration Register–NetConfig @ 0x04 (DIO) A-27. . . . . . . . . . . . . . .
A.3.6 Manufacturing Test Register–ManTest @ 0x04 (DIO) A-29. . . . . . . . . . . . . . . . . . .
A.3.7 Default PCI Parameter Registers–@ 0x08–0x0C (DIO) A-29. . . . . . . . . . . . . . . . .
A.3.8 General Address Registers–Areg_0-3 @ 0x10–0x24 (DIO) A-30. . . . . . . . . . . . . .
A.3.9 Hash Address Registers–HASH1/HASH2 @ 0x28–0x2C (DIO) A-31. . . . . . . . . .
A.3.10 Network Statistics Registers–@ 0x30–0x40 (DIO) A-32. . . . . . . . . . . . . . . . . . . . . .
A.3.11 Adapter Commit Register–Acommit @ 0x40 (DIO) (Byte 3) A-34. . . . . . . . . . . . . .
A.3.12 LED Register–LEDreg @ 0x44 (DIO) (Byte 0) A-35. . . . . . . . . . . . . . . . . . . . . . . . .
A.3.13 Burst Size Register–BSIZEreg @ 0x44 (DIO) (Byte 1) A-36. . . . . . . . . . . . . . . . . .
A.3.14 Maximum Rx Frame Size Register–MaxRx @ 0x44 (DIO) (Bytes 2+3) A-37. . .
A.3.15 Interrupt Disable Register - INTDIS @ 0x48 (DIO) (BYTE 0) A-38. . . . . . . . . . . . .
A.4 10Base-T PHY Registers A-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.4.1 PHY Generic Control Register–GEN_ctl @ 0x0 A-40. . . . . . . . . . . . . . . . . . . . . . . .
A.4.2 PHY Generic Status Register–GEN_sts @ 0x1 A-42. . . . . . . . . . . . . . . . . . . . . . . .
A.4.3 PHY Generic Identifier–GEN_id_hi/GEN_id_lo @ 0x2/0x3 A-44. . . . . . . . . . . . . . .
A.4.4 Autonegotiation Advertisement Register–AN_adv @ 0x4 A-45. . . . . . . . . . . . . . . .
A.4.5 Autonegotiation Link Partner Ability Register–AN_lpa @ 0x5 A-46. . . . . . . . . . . . .
A.4.6 Autonegotiation Expansion Register–AN_exp @ 0x6 A-47. . . . . . . . . . . . . . . . . . .
A.4.7 ThunderLAN PHY Identifier High/Low–TLPHY_id @ 0x10 A-48. . . . . . . . . . . . . . .
A.4.8 ThunderLAN PHY Control Register–TLPHY_ctl @ 0x11 A-49. . . . . . . . . . . . . . . . .
A.4.9 ThunderLAN PHY Status Register–TLPHY_sts @ 0x12 A-50. . . . . . . . . . . . . . . . .