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TP3094 COMBO

Quad PCM Codec/Filter

April 2003

TP3094 Quad PCM Codec/Filter

General Description

The TP3094 is a monolithic PCM Codec and Fil-

ter device implemented using a digital signal pro-

cessing architecture. It provides four voice

channels, combining transmit bandpass and re-

ceive low pass channel filters with companding A-

law or m-law PCM encoders and decoders. The

device is fabricated using National’s advanced

CMOS process.

The device includes anti-aliasing filters and sig-

ma-delta converters dedicated to each channel,

and by a common signal processing unit which

performs all the remaining filtering and process-

ing for the four channels.

The TP3094 includes a flexible PCM digital inter-

face, which allows the device to be connected to

PCM busses of different formats. It can also be

connected with other TP3094 devices in a cas-

cade fashion, for a system with up to 128 POTS

interfaces (when a 2.048MHz PCM bus is used).

Features

•Handles four voice channels

•Complete Codec and Filter system including:

- Transmit and receive channel filters

- A-law or

µ-law companding encoder/decoder

•Power down mode for low power consumption

•Compatible to standard time division multi-

plexed PCM bus

- 8 bit mode, frame signal from external reference

- 32 bit mode, internal TSA, with consecutive TS

•Up to 128 channels (32 devices) can be cas-

caded

•Programmable functions (common for all 4

channels):

- A-law or µ-law

- Single MCLK clock,automatically selectable from

8.192MHz, 4.096MHz, 2.048MHz and

1.536/1.544MHz

- Digital and Analog loopback test modes

•Designed for CCITT and LSSGR applications

•Single +5V power supply

•44 lead PLCC surface mount package

•Maximize line card circuit density

•Use in Central Office, Loop Carrier, and PBX

equipment subscriber line and trunk cards

•Wide operating temperature range

-40°C to

85°C

Connection Diagram

Order Number TP3094V

TP3094

6 5 4 3 2 1 44 43 42 41 40

18 19 20 21 22 23 24 25 26 27 28

PDN3

AVCC1

VRO3

GXO3

VXI3

PDN2

PDN1

PDN0

A/µLaw

MCLK

AGND1

VXI2

GXO2

VRO2

VRO1

GXO1

VXI1

AGND0

VXI0

GXO0

VRO0

AVCC0

PT1

PCMMode

PT2

TST

FSR0

FSX0

FSR1

FSX1

FSR2

FSX2

FSR3

FSX3

DVCC

DGND

PT4

PT3

See NS Package V44A

COMBO

and TRI-STATE

are registered trademarks of National Semiconductor Corporation

Summary of content (20 pages)

PAGE 1
TP3094 COMBO® Quad PCM Codec/Filter General Description Features • Handles four voice channels • Complete Codec and Filter system including: The TP3094 is a monolithic PCM Codec and Filter device implemented using a digital signal processing architecture. It provides four voice channels, combining transmit bandpass and receive low pass channel filters with companding Alaw or m-law PCM encoders and decoders. The device is fabricated using National’s advanced CMOS process.
PAGE 2
Simplified Block Diagram + VRO0 + VRO1 ADC + MCLK Digital Signal Processor PCM Interface ADC PCMMode ADC DAC TST A/u Law PDN0-3 Ref & Bias NF + DX DR FSX0-3 FSR0-3 TSx DAC PT3 PT4 VRO3 ClockDetection DAC VRO2 GXO3 VXI3- DAC PT2 GXO2 VXI2- PLL PT1 GXO1 VXI1- ADC AVCC0 AGND0 AVCC1 AGND1 DVCC DGND GXO0 VXI0- FIGURE 1. Simplified block diagram 2 www.national.
PAGE 3
Pin Descriptions signed transmit time-slots (for all four channels). MCLK (input) Master and PCM bit clock input. Must be either 1.536MHz/1.544MHz, 2.048MHz, 4.096MHz or 8.192MHz. Its value is automatically detected internally on power up with the valid frame sync input. DR (input) Receive PCM data input. Serial PCM data is shifted into the device on the falling edge of MCLK during the assigned receive time-slot. FSX0, FSR0 (inputs) Transmit and Receive Frame synchronization inputs for channel 0.
PAGE 4
Pin Descriptions (continued) Power Initialization When power is first applied to the device, poweron reset circuitry initializes the device and places it in the power down state. All non-essential circuits are de-activated. PCM output DX and analog outputs VRO0-3 are placed in the high impedance state, while FSX1 and FSR1 outputs are held low (in case 32-bit mode is selected). In the power down mode, power consumption is reduced to a minimum, typically 2mW.
PAGE 5
processing functions, such as PCM expansion according to the ALaw or uLaw and signal filtering. Then, for each channel it drives the Digital to Analog converter, through the proper interpolation stages and filters. Finally the signal is filtered and buffered to the output receive pin. The maximum output level voltage on the VRO pins on a load of 5kOhm+100pF is 1.12Vrms.
PAGE 6
Functional Description (continued) ignored. In case all the channels are placed in power down, the device will still generate the FS carry output on FSX1, FSR1. For timing diagrams refer to Fig.7 and Fig.8. 8-bit Mode In the 8-bit mode, PCM data is transferred independently for each of the four channels. Each channel has its dedicated transmit and receive frame signals, which determine the time-slots to be taken on the PCM bus. Both short sync and long sync frame are supported.
PAGE 7
Functional Description (continued) bypassing the low frequency filter. Test Modes Normal Operation Single Channel Digital Loopback Single Channel Analog Loopback Single Channel DC Conversion 4 Channels Digital Loopback 4 Channels Analog Loopback 4 Channels DC Conversion Invalid States TST 0 1 1 1 1 1 1 1 PDN0 x 1 0 1 0 0 0 0 PDN1 x 1 1 0 0 0 0 0 PDN2 x A0 A0 A0 0 0 1 1 PDN3 x A1 A1 A1 0 1 0 1 Description Ch. select with PDN2, PDN3 Ch. select with PDN2, PDN3 Ch.
PAGE 8
Timing Diagrams MCLK 125µS FSX3 or FSR3 FSX2 or FSR2 FSX0 or FSR0 DX D7 CH3 D0 D7 CH2 D0 D7 CH1 D0 D7 CH0 D0 DR D7 CH3 D0 D7 CH2 D0 D7 CH1 D0 D7 CH0 D0 TSX FIGURE 2. Timing diagram for PCM Interface, 8-bit mode (Long Frame Sync) tWMH tPM tFM MCLK tRM tWML FIGURE 3.
PAGE 9
Timing Diagrams (continued) MCLK 125µS FSX3 or FSR3 FSX2 or FSR2 FSX0 or FSR0 DX D7 CH3 D0 D7 CH2 D0 D7 CH1 D0 D7 CH0 D0 DR D7 CH3 D0 D7 CH2 D0 D7 CH1 D0 D7 CH0 D0 TSX FIGURE 5. Timing diagram for PCM Interface, 8-bit mode (Short Frame Sync) TSX tTSZC tDBTS MCLK 1st FSX or t SF 2nd 3rd 5th 4th 6th 7th 9th 8th tHF FSR tDBD DX tDBD D7 (Sign) tDZC D6 (MSB) t SDB DR D7 (Sign) D6 (MSB) D4 D5 D2 D3 D1 D0 (LSB) tHDB D5 D4 D3 D2 D1 D0 (LSB) FIGURE 6.
PAGE 10
Timing Diagrams (continued) MCLK 125µS FSX0 or FSR0 FSX1 or FSR1 D7CH0 D0 D7 CH1 D0 D7 CH2 D0 D7 CH3 D0 DX DR D7CH0 D0 D7 CH1 D0 D7 CH2 D0 D7 CH3 D0 TSX FIGURE 7. Timing diagram for PCM Interface, 32-bit mode TSX tTSZC tDBTS MCLK 1st FSX0 or tSF 2nd 3rd 33th 32th 5th 4th tHF tDOFL FSR0 tDOFH FSX1 or FSR1 tDBD tDBD DX D7-0 (Sign) D6-0 (MSB) tDZC tSDB DR D7-0 (Sign) D6-0 (MSB) D0-3 (LSB) D4-0 D5-0 tHDB D5-0 D4-0 D1-3 D0-3 (LSB) FIGURE 8.
PAGE 11
Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. 7V VCC to DGND Voltage at any digital inputs or outputs VCC +0.3V to DGND -0.3V Voltage at any analog inputs or outputs VCC +0.3V to AGND-0.
PAGE 12
Electrical Characteristics (continued) Symbol Parameter Power Dissipation ICC0 Power down current (all channels down) ICC1 Power up active current (all channel active) Amplitude Response Absolute Levels tmax Virtual decision value defined per ITU G.711 Conditions Min Typ Max Units Measured after having first achieved power-up state. MCLK=2.048MHz No load, MCLK=2.048MHz 0.9 1.5 mA 35 50 mA Nominal 0dBm0 level is 0dBm at the analog inputs/outputs Max overload level 3.17dBm0 (µ-law) 3.
PAGE 13
Electrical Characteristics (continued) Symbol Parameter Conditions Min GRAL Receive gain variation with level Sinusoidal test method, PCM level=-40dBm0 to +3dBm0 PCM Level=-50dBm0 to -40dBm0 PCM Level=-55dBm0 to -50dBm0 -0.2 -0.4 -1.0 Typ Max Units 0.2 0.4 1.0 dB dB dB Note 2: Measure voiceband image signal, stimulus signal level is -25dBm0.
PAGE 14
Electrical Characteristics (continued) Symbol Parameter Envelope delay distortion Transmit delay, absolute DXA DXR Transmit delay, relative to DXA DRA Receive delay, absolute DRR Receive delay, relative to DRA Noise NXP Transmit Idle channel noise, A-law NXC Transmit Idle channel noise, µ-law NRP Receive Idle channel noise, A-law NRC Receive Idle channel noise, µ-law NXR Analog to Analog Noise Power supply rejection Positive power supply PPSRX rejection, transmit PPSRR Positive power sup
PAGE 15
Electrical Characteristics (continued) Symbol Parameter Conditions Min Typ Max Units CTR-X Receive to transmit crosstalk (Intra-channel Crosstalk) CTFEX Far end crosstalk with analog stimulus (Interchannel crosstalk) PCM code for stimulated channel equals to 0dBm0, 300Hz3.4KHz, PCM code for all other channels equals to positive zero, FSX=FSR, Measure PCM response.
PAGE 16
Timing Specifications Symbol Parameter Conditions Min Typ Max Units 60 MHz MHz MHz MHz MHz % 10 ns 10 ns Clock and Data Timing All timing parameters are measured at VOH=2.0V and VOL=0.
PAGE 17
Applications Information System Bus +5V Supply AVCC0 AVCC1 DVCC GX0 DX DR VXI0 Tip SLIC Zb Ring VRO0 GX11 Tip VXI1 SLIC Zb Ring VRO1 GX2 Tip FSX0 FSR0 T P 3 0 9 4 PDN0 FSX1 FSR1 PDN1 FSX2 FSR2 PDN2 VXI2 SLIC Zb Ring FSX3 FSR3 PDN3 VRO2 GX3 Tip SLIC Ring PCM Mode VXI3 Zb TSX VRO3 MCLK NF DGND A/ULaw AGND0 AGND1 5V (A-law) DGND (u-law) FIGURE 9. Typical application in a non cascaded mode 17 www.national.
PAGE 18
Applications Information To additional TP3094 COMBOs +5V Supply System Bus AVCC0 AVCC1 DVCC GX0 DX DR VXI0 Tip SLIC Zb Ring FSX0 VRO0 GX11 Tip VXI1 SLIC Zb Ring VRO1 GX2 Tip FSR0 T P 3 0 9 4 PDN0 FSX1 FSR1 PDN1 FSX2 FSR2 PDN2 VXI2 SLIC Zb Ring FSX3 FSR3 PDN3 VRO2 GX3 5V Tip VXI3 SLIC PCM Mode Zb Ring TSX VRO3 MCLK NF DGND A/ULaw AGND0 5V (A-law) DGND (u-law) AGND1 +5V Supply AVCC0 AVCC1 DVCC GX0 DX DR VXI0 Tip SLIC Zb Ring FSX0 VRO0 GX11 Tip VXI1 SLIC
PAGE 19
TP3094 Quad PCM Codec/Filter Physical Dimensions inches (millimeters) unless otherwise noted 44-Lead Molded Plastic Chip Carrier (PLCC) Order Number TP3094V NS Package Number V44A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.
PAGE 20
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.