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NRND

TP3404

www.ti.com

SNOS703 –DECEMBER 2004

TP3404 Quad Digital Adapter for Subscriber Loops (QDASL)

Check for Samples: TP3404

FEATURES

DESCRIPTION

The TP3404 is a combination 4-line transceiver for

• 4 COMPLETE ISDN PBX 2-WIRE DATA

voice and data transmission on twisted pair

TRANSCEIVERS INCLUDING:

subscriber loops, typically in PBX line card

• Quad 2 B Plus D Channel Interface for PBX

applications. It is a companion device to the

“U” Interface

TP3401/2/3 DASL single-channel transceivers. In

addition to 4 independent transceivers, a time-slot

• 144 kb/s Full-Duplex on 1 Twisted Pair Using

assignment circuit is included to support interfacing to

Burst Mode Transmission Technique

the system backplane.

• Loop Range up to 6 kft (#24AWG)

Each QDASL line operates as an ISDN “U” Interface

• Alternate Mark Inversion Coding with Transmit

for short loop applications, typically in a PBX

Pulse Shaping DAC, Smoothing Filter, and

environment, providing transmission for 2 B channels

Scrambler for Low Emi Radiation

and 1 D channel.

• Adaptive Line Equalizer

Full-duplex transmission at 144 kb/s is achieved on

• On-Chip Timing Recovery, No External

single twisted wire pairs using a burst-mode

Components

technique (Time Compression Multiplexed). All timing

• Programmable Time-Slot Assignment TDM

sequences necessary for loop activation and de-

Interface for B Channels

activation are generated on-chip.

• Separate Interface for D Channel with

Alternate Mark Inversion (AMI) line coding is used to

Programmable Sub-Slot Assignment

ensure low error rates in the presence of noise with

lower emi radiation than other codes such as Biphase

• 4.096 MHz Master Clock

(Manchester). On #24 AWG cable the range is at

• 4 Loop-Back Test Modes

least 1.8 km (6k ft.).

• MICROWIRE™ Compatible Serial Control

Interface

• 5V Operation

• 28-Pin PLCC Package

BLOCK DIAGRAM

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2MICROWIRE is a trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (19 pages)

PAGE 1
NRND TP3404 www.ti.com SNOS703 – DECEMBER 2004 TP3404 Quad Digital Adapter for Subscriber Loops (QDASL) Check for Samples: TP3404 FEATURES DESCRIPTION • The TP3404 is a combination 4-line transceiver for voice and data transmission on twisted pair subscriber loops, typically in PBX line card applications. It is a companion device to the TP3401/2/3 DASL single-channel transceivers.
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NRND TP3404 SNOS703 – DECEMBER 2004 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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NRND TP3404 www.ti.com SNOS703 – DECEMBER 2004 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise specified, limits printed in BOLD characters are specified for VCCA = VCCD = 5V ±5%, TA = 0°C to +70°C. Typical characteristics are specified at VDDA = VDDD = 5.0V, TA = 25°C. All signals are referenced to GND, which is the common of GNDA and GNDD Symbol Parameter Conditions Min Typ Max Units 4.096 4.
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NRND TP3404 SNOS703 – DECEMBER 2004 www.ti.com PIN DESCRIPTIONS Pin Pin No. Name 4 Description 1 GNDA Analog Ground or 0V. All analog signals are referenced to this pin. 15 GNDD Digital Ground 0V. It must connect to GNDA with a shortest possible trace. This can be done directly underneath the part. 28 VDDA Positive power supply input to QDASL analog section. It must be 5V ±5%. 16 VDDD Positive power supply input to QDASL digital section.
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NRND TP3404 www.ti.com SNOS703 – DECEMBER 2004 Li1 GNDA VDDA 3 2 1 28 27 26 Lo2 Lo1 4 Li2 Lo0 CONNECTION DIAGRAM Li0 5 25 Lo3 NC 6 24 Li3 DI 7 23 NC DO 8 22 NC* MCLK 9 21 CI BCLK 10 20 CO FS 11 19 CCLK CS INT VDDD GNDD TSB BI BO 12 13 14 15 16 17 18 * Do not connect to this pin. Figure 1.
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NRND TP3404 SNOS703 – DECEMBER 2004 www.ti.com FUNCTIONAL DESCRIPTION The QDASL contains 4 transceivers, each of which can interoperate with any of the TP340X family of singlechannel DASL transceivers. Each QDASL transceiver has its own independent line transmit and receive section, timing recovery circuit, scrambler/descrambler and loop activation controller. Functions which are shared by the 4 transceivers include the Microwire control port and the digital interface with time-slot assignment.
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NRND TP3404 www.ti.com SNOS703 – DECEMBER 2004 LINE RECEIVE SECTIONS The input of each receive section, Li0–Li3, consists of a continuous anti-alias filter followed by a switchedcapacitor low-pass filter designed to limit the noise bandwidth with minimum intersymbol interference.
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NRND TP3404 SNOS703 – DECEMBER 2004 www.ti.com ACTIVATION AND LOOP SYNCHRONIZATION Activation (i.e. power-up and loop synchronization) may be initiated from either end of the loop. If the master (QDASL) end is activating the loop, it sends normal bursts of scrambled “1”s which are detected by the slave's line-signal-detect circuitry.
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NRND TP3404 www.ti.com SNOS703 – DECEMBER 2004 Table 2.
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NRND TP3404 SNOS703 – DECEMBER 2004 www.ti.com – This loop will transfer all data (2B+D) received at BI/DI back to BO/DO. The data is also transmitted to the line. TIME-SLOT ASSIGNMENT The digital interface of the QDASL uses time-division multiplexing, with data framed in up to 64 possible 8-bit time-slots per 125 μs frame. Channels B1 and B2 for all 4 lines are clocked in (towards the line) at the BI pin and clocked out (from the line) at the BO pin.
PAGE 11
NRND TP3404 www.ti.com SNOS703 – DECEMBER 2004 When the transmit direction (towards the line) is disabled there will be all “ONE's” (scrambled) as data for this channel at the Lo pin. If the receive direction (from the line) is disabled, BO will stay high impedance for the programmed time slot while, if it is enabled, data out on BO in the assigned time slot is the data from Li. BITS 5–0: TS5–TS0 These bits define the binary number of the time-slot selected. Time-slots are numbered from 0–63.
PAGE 12
NRND TP3404 SNOS703 – DECEMBER 2004 www.ti.com Table 6.
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NRND TP3404 www.ti.com SNOS703 – DECEMBER 2004 APPLICATIONS INFORMATION POWER SUPPLIES While the pins of the TP3404 QDASL device are well protected against electrical misuse, it is recommended that the standard CMOS practice of applying GND to the device before any other connections are made should always be followed. In applications where the printed circuit card may be plugged into a hot socket with power and clocks already present, an extra long ground pin on the connector should be used.
PAGE 14
NRND TP3404 SNOS703 – DECEMBER 2004 www.ti.com Figure 6.
PAGE 15
NRND TP3404 www.ti.com SNOS703 – DECEMBER 2004 Figure 7. Microwire Control Interface Timing Details Figure 8. B Channel Digital Interface Details Figure 9.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 17
PACKAGE OPTION ADDENDUM www.ti.com 30-Oct-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.
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