User Manual

ManualsBrandsTexas Instruments ManualsReceivers and AmplifiersTPA3200D1

www.ti.com

FEATURES DESCRIPTION

LRCK

1.0 mF

Control

Inputs

DGND

Gain Select

+5V

Channel Select

{

BCK

GAIN0

VCOM

DATA

FORMAT

SCLK

GAIN1

LR_SEL

VDD

SHUTDOWN

VCLAMP

PGND

Shutdown Control

+18V

MUTE

DEMP

ZERO

AVCC

10 mF

{

Zero Input Flag

FLT1

FLT2

22 nF

COSC

AGND

ROSC

VREF

BYPASS

220 pF

1 mF

120 kW

0.22 mF

BSN

51 W

OUTN

0.22 mF

BSP

OUTP

51 W

PVCC

Digital Audio

Processor

TPA3200D1

S or 16-bit RJ

TAS3103

TPA3200D1

SLOS442A – MAY 2005 – REVISED JULY 2005

20-W MONO DIGITAL INPUT AUDIO AMPLIFIER

• Digital Interface

The TPA3200D1 is a 20-W (per channel) efficient,

digital audio power amplifier for driving a bridged-tied

– 24-bit Resolution

speaker. The TPA3200D1 can drive a speaker with

– Supports I

S and 16-Bit Word

an impedance as low as 4 Ω . The high efficiency of

Right-Justified Digital Input Formats

the TPA3200D1 (85%) eliminates the need for an

– Multiple Sampling Frequencies:

external heat sink.

5 kHz – 200 kHz

The digital input accepts 16-24 bit data in I

S format

– 8x Oversampling Digital Filter

or 16-bit word right-justified. A digital filter performs

– Soft Mute

an 8x interpolation function. Other features include

soft mute, a zero input detect output flag for power

• Power Amplifier

conscious designs, and power saving shutdown

– 20-W into an 8- Ω Load from an 18-V Supply

mode.

– Efficient Operation Eliminates Need for Heat

Sinks

– Three Selectable, Fixed Gain Settings

– Thermal and Short-Circuit Protection

Simplified Application Circuit

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (30 pages)

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TPA3200D1 www.ti.
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TPA3200D1 www.ti.com SLOS442A – MAY 2005 – REVISED JULY 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE OPTIONS (1) TA PACKAGED DEVICE 44-PIN (DCP) (1) –40°C to 85°C TPA3200D1DCP The DCP package is available taped and reeled. To order a taped and reeled part, add the suffix R to the part number (e.g., TPA3200D1DCPR).
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TPA3200D1 www.ti.com SLOS442A – MAY 2005 – REVISED JULY 2005 RECOMMENDED OPERATING CONDITIONS PARAMETER PIN NAME MIN PVCC, VCC VSS Supply voltage VIH High-level input voltage SHUTDOWN, GAIN0, GAIN1, BCK, SCLK, DATA, LRCK, FORMAT, MUTE, DEMP VIL Low-level input voltage SHUTDOWN, GAIN0, GAIN1, BCK, SCLK, DATA, LRCK, FORMAT, MUTE, DEMP VIH High-level input voltage LR_SEL VIL Low-level input voltage LR_SEL IIH High-level input current IIL Low-level input current VDD MAX 8 18 4.5 5.
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TPA3200D1 www.ti.com SLOS442A – MAY 2005 – REVISED JULY 2005 FORMAT CHARACTERISTICS All specifications at TA = 25°C, VDD = 5 V, fS = 44.
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TPA3200D1 www.ti.
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TPA3200D1 www.ti.
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TPA3200D1 www.ti.com SLOS442A – MAY 2005 – REVISED JULY 2005 Terminal Functions TERMINAL NO. NAME I/O DESCRIPTION 1 BCK I Bit clock input for audio data 3 DATA I Audio data input 4 LRCK I Left and right channel audio data latch enable input 7 LR_SEL I Select left-channel or right-channel data HIGH: Left channel active LOW: Right channel active 11 GAIN0 I Gain select least significant bit. TTL logic levels with compliance to 5 V. 12 GAIN1 I Gain select most significant bit.
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TPA3200D1 www.ti.com SLOS442A – MAY 2005 – REVISED JULY 2005 TYPICAL CHARACTERISTICS Total Harmonic Distortion Plus Noise vs Output Power Total Harmonic Distortion Plus Noise vs Output Power 10 VCC = 12 V RL = 8 Gain = 18 dB fS = 48 kHz 24−bit, I2S format 5 2 Total Hormonic Distortion Plus Noise − % Total Hormonic Distortion Plus Noise − % 10 1 0.5 10 kHz 0.2 0.1 1 kHz 0.05 0.02 20 Hz 0.01 10m 100m 200m 1 2 VCC = 12 V RL = 8 Gain = 23.6 dB fS = 48 kHz 24−bit, I2S format 5 2 1 0.
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TPA3200D1 www.ti.com SLOS442A – MAY 2005 – REVISED JULY 2005 TYPICAL CHARACTERISTICS (continued) Total Harmonic Distortion Plus Noise vs Frequency Total Harmonic Distortion Plus Noise vs Frequency 20 VCC = 12 V RL = 8 Gain = 18 dB fS = 48 kHz 24−bit, I2S format 10 5 2 1 PO = 5 W 0.5 0.2 0.1 PO = 500 mW 0.05 PO = 1 W 0.02 0.01 20 100 200 1k 2k Total Hormonic Distortion Plus Noise − % Total Hormonic Distortion Plus Noise − % 20 10 VCC = 12 V RL = 8 Gain = 23.
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TPA3200D1 www.ti.com SLOS442A – MAY 2005 – REVISED JULY 2005 TYPICAL CHARACTERISTICS (continued) Total Harmonic Distortion vs Frequency Power Supply Voltage Rejection Ratio vs Frequency 0 VCC = 12 V RL = 4 Ù Gain = 18 dB fS = 48 kHz 2 24-Bit, I S format 5 2 PSRR − Power Supply Rejecyion Ratio − dB THD + N - Total Harmonic Distortion + Noise - % 10 1 Po = 2 W 0.5 Po = 200 mW 0.2 0.1 0.05 Po = 7.5 W 0.02 −10 −20 −30 −40 −50 −60 0.
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TPA3200D1 www.ti.com SLOS442A – MAY 2005 – REVISED JULY 2005 TYPICAL CHARACTERISTICS (continued) Maximum Output Power vs Load Impedance Maximum Output Power vs Load Impedance 21 21 TA = 60°C TA = 45°C 19 VCC = 18 V PO − Maximum Output Power − W PO − Maximum Output Power − W 19 17 15 VCC = 15 V 13 11 9 VCC = 12 V 7 VCC = 18 V 15 VCC = 15 V 13 11 9 VCC = 12 V 7 5 3.6 4 5 6 7 8 ZL − Load Impedance − Ω 9 5 3.6 10 4 5 6 7 8 ZL − Load Impedance − Ω Figure 13. Figure 14.
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TPA3200D1 www.ti.com SLOS442A – MAY 2005 – REVISED JULY 2005 APPLICATION INFORMATION 2 { I S/RJ Clocks & Data BCK SCLK FORMAT NC VDD 10 mF DATA MUTE LRCK DEMP DGND DGND VDD ZERO LR_SEL DGND VDD Control Inputs Zero Flag Output FLT1 DGND 0.1 mF } 22 nF FLT2 VCOM VCC GAIN0 VREF GAIN1 BYPASS 10 mF Gain Control { Shutdown Control 1 mF 1 mF SHUTDOWN COSC PGND ROSC VCLAMP AGND NC AGND 220 pF 120 kW 1 mF 51 W 0.22 mF BSN BSP 0.
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TPA3200D1 www.ti.com SLOS442A – MAY 2005 – REVISED JULY 2005 APPLICATION INFORMATION (continued) SYSTEM CLOCK INPUT The TPA3200D1 requires a system clock for operating the digital interpolation filters and multilevel delta-sigma modulators. The system clock is applied at the SCLK input (pin 44). Table 1 shows examples of system clock frequencies for common audio sampling rates. Figure 18 shows the timing requirements for the system clock input.
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TPA3200D1 www.ti.com SLOS442A – MAY 2005 – REVISED JULY 2005 AUDIO DATA FORMATS AND TIMING The TPA3200D1 supports I2S and 16-bit-word right-justified. The data formats are shown in Figure 20. Data formats are selected using the FORMAT pin on the TPA3200D1. All formats require binary 2s-complement, MSB-first audio data. Figure 19 shows a detailed timing diagram for the serial audio interface. 1.4 V LRCK t(BCH) t(BCL) t(LB) 1.4 V BCK t(BCY) t(BL) 1.4 V DATA t(DS) t(DH) Figure 19.
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TPA3200D1 www.ti.
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TPA3200D1 www.ti.com SLOS442A – MAY 2005 – REVISED JULY 2005 REGISTER CONTROL The digital functions of the TPA3200D1 are controlled by 4 terminals. Table 2 shows selectable data formats, Table 3 shows de-emphasis control, Table 4 shows mute control, and Table 5 shows channel-output select. Table 2. Data Format Select FMT (PIN 43) DATA FORMAT LOW 16- to 24-bit, I2S format HIGH 16-bit right-justified Table 3. De-Emphasis Control DEMP (PIN 41 ) DE-EMPHASIS FUNCTION LOW 44.
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TPA3200D1 www.ti.com SLOS442A – MAY 2005 – REVISED JULY 2005 CLASS-D OPERATION This section focuses on the class-D operation of the TPA3200D1. Traditional Class-D Modulation Scheme The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output where each output is 180 degrees out of phase and changes from ground to the supply voltage, VCC.
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TPA3200D1 www.ti.com SLOS442A – MAY 2005 – REVISED JULY 2005 TPA3200D1 Modulation Scheme The TPA3200D1 uses a modulation scheme that still has each output switching from ground to VCC. However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and OUTN is greater than 50% for negative output voltages.
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TPA3200D1 www.ti.com SLOS442A – MAY 2005 – REVISED JULY 2005 Maximum Allowable Output Power (Safe Operating Area) The TPA3200D1 can drive load impedances as low as 3.6 Ω from power supply voltages ranging from 8 V to 18 V. To prevent device failure, however, the output power of the TPA3200D1 must be limited. Figure 23 shows the maximum allowable output power versus load impedance for three power supply voltages at an ambient temperature of 25°C.
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TPA3200D1 www.ti.com SLOS442A – MAY 2005 – REVISED JULY 2005 Ferrite Chip Bead OUTP 1 nF 4 W or Greater Ferrite Chip Bead OUTN 1 nF Figure 24. Typical Ferrite Chip Bead Filter (Chip bead example: Fair-Rite 2512067007Y3) 15 µH Ferrite Chip Bead OUTP 1 µF 15 µH 0.22 µF 1 nF Ferrite Chip Bead 4Ω OUTN 0.22 µF 1 nF Figure 25. Typical LC Output Filter for 4-Ω Speaker, Cutoff Frequency of 41 kHz 33 µH Ferrite Chip Bead OUTP 0.47 µF 33 µH 0.1 µF 1 nF Ferrite Chip Bead 8Ω OUTN 0.
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TPA3200D1 www.ti.com SLOS442A – MAY 2005 – REVISED JULY 2005 THERMAL PROTECTION Thermal protection on the TPA3200D1 prevents damage to the device when the internal die temperature exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 15°C.
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TPA3200D1 www.ti.com SLOS442A – MAY 2005 – REVISED JULY 2005 The typical output voltage, measured across the load, is also given in Table 6 at each of the gain steps. This is the expected voltage with a full scale input signal applied at the digital inputs and VDD = 5 V. This voltage scales proportionally with a lower or higher VDD. For example, if VDD = 4.5 V, scale the results in Table 6 by 4.5/5, or 0.9.
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TPA3200D1 www.ti.com SLOS442A – MAY 2005 – REVISED JULY 2005 SHUTDOWN OPERATION The TPA3200D1 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute minimum level during periods of non-use for battery-power conservation. The SHUTDOWN input terminal should be held high during normal operation when the amplifier is in use. Pulling SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state, ICC(SD) = 1 µA.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPA3200D1DCPR Package Package Pins Type Drawing SPQ HTSSOP 2000 DCP 44 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 24.4 Pack Materials-Page 1 6.8 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 11.7 1.6 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPA3200D1DCPR HTSSOP DCP 44 2000 367.0 367.0 45.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.