Datasheet

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TPA5050

www.ti.com

FEATURES APPLICATIONS

DESCRIPTION

SIMPLIFIED APPLICATION DIAGRAM

BCLK

LRCLK

DATA DATA_OUT

3.3V

BCLK

LRCLK

DATA

TPA5050

Digital Amplifier

SCLK

AudioProcessor

SCLK

BCLK

LRCLK

DATA

SDA

SCL

ADDx

(2:0)

I CDelay

Control

VDD

GND

TAS3103A

ATSC

Processor

TAS5504A

+TAS5122

TPA5050

SLOS492B – MAY 2006 – REVISED MAY 2007

STEREO DIGITAL AUDIO LIP-SYNC DELAY WITH I

C CONTROL

• High Definition TV Lip-Sync Delay

• Digital Audio Formats: 16-24-bit I

Right-Justified, Left-Justified

• Flat Panel TV Lip-Sync Delay

• Home Theater Rear-Channel Effects

• I

C Bus Controlled

• Wireless Speaker Front-Channel

• Single Serial Input Port

Synchronization

• Delay Time: 170 ms/ch at fs = 48 kHz

• Delay Resolution: One Sample

• Delay Memory Cleared on Power-Up or After

The TPA5050 accepts a single serial audio input,

Delay Changes

buffers the data for a selectable period of time, and

– Eliminates Erroneous Data From Being

outputs the delayed audio data on a single serial

Output

output. One device allows delay of up to 170 ms/ch

(fs = 48 kHz) to synchronize the audio stream to the

• 3.3 V Operation With 5 V Tolerant I/O and I

video stream in systems with complex video

Control

processing algorithms. If more delay is needed, the

• Supports Audio Bit Clock Rates of 32 to 64 fs

devices can be connected in series.

with fs = 32 kHz–192 kHz

• No external crystal or oscillator required

– All Internal Clocks Generated From the

Audio Clock

• Surface Mount 4mm × 4mm, 16-pin QFN

Package

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (22 pages)

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0 05 A5 TP TPA5050 www.ti.com SLOS492B – MAY 2006 – REVISED MAY 2007 STEREO DIGITAL AUDIO LIP-SYNC DELAY WITH I2C CONTROL FEATURES APPLICATIONS • • • • • • • • • • • • • • Digital Audio Formats: 16-24-bit I2S, Right-Justified, Left-Justified I2C Bus Controlled Single Serial Input Port Delay Time: 170 ms/ch at fs = 48 kHz Delay Resolution: One Sample Delay Memory Cleared on Power-Up or After Delay Changes – Eliminates Erroneous Data From Being Output 3.
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TPA5050 www.ti.com SLOS492B – MAY 2006 – REVISED MAY 2007 PIN DESCRIPTIONS BCLK DATA_OUT GND VDD 16 15 14 13 RSA (QFN) PACKAGE (TOP VIEW) SCL 3 10 ADD0 SDA 4 9 GND 8 ADD1 GND 11 7 2 GND DATA 6 ADD2 GND 12 5 1 GND LRCLK TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. ADD0 10 I I2C address select pin – LSB ADD1 11 I I2C address select pin ADD2 12 I I2C address select pin – MSB BCLK 16 I Audio data bit clock input for serial input. 5V tolerant input.
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TPA5050 www.ti.com SLOS492B – MAY 2006 – REVISED MAY 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature (unless otherwise noted) VDD VI (1) Supply voltage Input voltage DATA, LRCLK, BCLK, SCL, SDA ADD[2:0] VALUE UNIT –0.3 to 3.6 V –0.3 to 5.5 V –0.3 to VDD+0.
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TPA5050 www.ti.com SLOS492B – MAY 2006 – REVISED MAY 2007 DC CHARACTERISTICS TA = 25°C, VDD = 3 V (unless otherwise noted) PARAMETER TEST CONDITIONS IDD Supply current IOH High-level output current DATA_OUT = 2.6 V IOL Low-level output current MIN TYP MAX 1.5 3 mA 7 13 mA 7 13 mA VDD = 3.3 V, fs = 48 kHz, BCLK = 32 fs IIH High-level input current IIL Low-level input current DATA_OUT = 0.4 V DATA, LRCLK, BCLK, SCL, SDA, Vi = 5.5V, VDD = 3V 20 ADD[2:0], Vi = 3.6V, VDD = 3.
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TPA5050 www.ti.com SLOS492B – MAY 2006 – REVISED MAY 2007 Serial Audio Input Ports over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS fSCLKIN Frequency, BCLK 32 × fs, 48 × fs, 64 × fs MIN TYP 1.024 MAX UNIT 12.
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TPA5050 www.ti.
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TPA5050 www.ti.com SLOS492B – MAY 2006 – REVISED MAY 2007 APPLICATION INFORMATION (continued) 2 GENERAL I C OPERATION The I2C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte (8-bit) format with the most-significant bit (MSB) transferred first.
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TPA5050 www.ti.com SLOS492B – MAY 2006 – REVISED MAY 2007 The TPA5050 supports sequential I2C addressing. For write transactions, if a register is issued followed by data for that register and all the remaining registers that follow, a sequential I2C write transaction has taken place.
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TPA5050 www.ti.com SLOS492B – MAY 2006 – REVISED MAY 2007 Repeat Start Condition Start Condition Acknowledge A6 A5 A1 A0 R/W ACK A7 I2C Device Address and Read/Write Bit Acknowledge A6 A5 A4 A0 ACK Not Acknowledge Acknowledge A6 A5 A1 A0 R/W ACK D7 D6 I2C Device Address and Read/Write Bit Register D1 D0 ACK Stop Condition Data Byte Figure 8.
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TPA5050 www.ti.com SLOS492B – MAY 2006 – REVISED MAY 2007 SERIAL CONTROL INTERFACE REGISTER SUMMARY Table 2. Serial Control Register Summary REGISTER REGISTER NAME NO.
PAGE 11
TPA5050 www.ti.com SLOS492B – MAY 2006 – REVISED MAY 2007 If the result of the formula above is greater than the maximum number of delay samples (8191 for TPA5050), then the value is limited to this maximum before passing to the delay block. Table 5. Frame Delay Registers (0x06) (1) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0 Settings in this register are masked and audio delay is determined by settings in the right/left audio delay registers.
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TPA5050 www.ti.com SLOS492B – MAY 2006 – REVISED MAY 2007 Table 7. Complete Update Registers (0x08) (1) D7–D1 (1) D0 FUNCTION X 0 No data from the register settings is passed to the delay block. X 1 Stream type, right/left delay or frame delay, and packet length is passed to the delay functional block. Default values are in bold. APPLICATION EXAMPLES The following are some examples of I2C commands used to read or write to the TPA5050.
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TPA5050 www.ti.com SLOS492B – MAY 2006 – REVISED MAY 2007 Single Byte Read In this example, one byte of data is read from the Control Register (0x01). After the data (represented xx) by is read by the master device, the master device issues a Not Acknowledge, before stopping the communication.
PAGE 14
TPA5050 www.ti.com SLOS492B – MAY 2006 – REVISED MAY 2007 DEVICE CURRENT CONSUMPTION The TPA5050 draws different amounts of supply current depending upon the conditions under which it is operated. As VDD increases, so too does IDD. Likewise, as VDD decreases, IDD decreases. The same is true of the sampling frequency, fs. An increase in fs causes an increase in IDD. Figure 11 illustrates the relationship between operating condition and typical supply current.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPA5050RSAR QFN RSA 16 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 TPA5050RSAT QFN RSA 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPA5050RSAR QFN RSA 16 3000 367.0 367.0 35.0 TPA5050RSAT QFN RSA 16 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.