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1 2 3 4

DDC Line Switching

4.0 5.0 6.0 7.0 8.0 9.0 10.0

Time (uSec)

Voltage (V)

TPD12S015A DDC Translator

FET Switch Translator

DDC Line Switching

4.0 5.0 6.0 7.0 8.0 9.0 10.0

Time (uSec)

Voltage (V)

TPD12S015A DDC Translator

FET Switch Translator

TPD12S015A

www.ti.com

SLLSE74C –JUNE 2011–REVISED MARCH 2013

HDMI COMPANION CHIP WITH STEP-UP DC-DC, I

C LEVEL SHIFTER, AND HIGH-SPEED

ESD CLAMPS

Check for Samples: TPD12S015A

FEATURES

• Conforms to HDMI Compliance Tests Without • Improved Drop-in Replacement for the

Any External Components Industry Popular TPD12S015

• Supports HDMI 1.4 Data Rate • Industrial Temperature Range: -40°C to 85°C

• Match Class D and Class C Pin Mapping

APPLICATIONS

• Excellent Matching Capacitance (0.05pF) in

• Smart Phones

Each Differential Signal Pair

• eBook

• Internal Boost Converter to Generate 5V From

a 2.3-5.5V Battery Voltage

• Tablet PC

• Auto-direction Sensing Level Shifting in the

• Digital Camcorders

CEC, SDA, and SCL Paths

• Portable Game Console

• IEC 61000-4-2 (Level 4) System Level ESD

• Digital Still Cameras

Compliance

SPACE

YFF PACKAGE

(TOP VIEW)

Figure 1. SCL_B or SDA_B Buffers of

TPD12S015A Driving Long

For package dimensions, see the

HDMI Cable (750pF Load)

Mechanical Drawing at the end of this

document.

YFF PACKAGE PIN MAPPING

1 2 3 4

A LS_OE V

CCA

D2+ D2–

B SCL_A CEC_A GND D1+

C SDA_A HPD_A GND D1–

D CT_CP_HPD GND CEC_B D0+

E FB GND SCL_B D0–

F 5VOUT SW SDA_B CLK+

G P

GND

BAT

HPD_B CLK–

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (34 pages)

PAGE 1
TPD12S015A www.ti.com SLLSE74C – JUNE 2011 – REVISED MARCH 2013 HDMI COMPANION CHIP WITH STEP-UP DC-DC, I2C LEVEL SHIFTER, AND HIGH-SPEED ESD CLAMPS Check for Samples: TPD12S015A FEATURES 1 • Conforms to HDMI Compliance Tests Without Any External Components Supports HDMI 1.4 Data Rate Match Class D and Class C Pin Mapping Excellent Matching Capacitance (0.05pF) in Each Differential Signal Pair Internal Boost Converter to Generate 5V From a 2.3-5.
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TPD12S015A SLLSE74C – JUNE 2011 – REVISED MARCH 2013 www.ti.com DESCRIPTION/ORDERING INFORMATION The TPD12S015A is an integrated HDMI companion chip solution. This device offers 8 low capacitance ESD clamps allowing HDMI 1.4 data rates. The 0.4-mm pitch WCSP package pin mapping matches the HDMI Type D or Type C connectors. The integrated ESD clamps in monolithic silicon technology provide good matching between each differential signal pair.
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TPD12S015A www.ti.com SLLSE74C – JUNE 2011 – REVISED MARCH 2013 SYSTEM LEVEL BLOCK DIAGRAM Application Schematics for HDMI controllers with one GPIO for HDMI Interface Control 1.2V to 3.3V 0.
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TPD12S015A SLLSE74C – JUNE 2011 – REVISED MARCH 2013 www.ti.com Application Schematics for HDMI controllers with TOW GPIOs for HDMI Interface Control 1.2V to 3.3V CT_CP_HPD VCCA 0.
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TPD12S015A www.ti.com SLLSE74C – JUNE 2011 – REVISED MARCH 2013 CIRCUIT BLOCK DIAGRAM VBAT FB (IEC) SW CT_CP_HPD 5VOUT (IEC) 5V DC/DC 470k PGND Dx+, DxCLK+, CLK8 (IEC) HDMI ESD Clamp (x8) LS_OE_INTERNAL 5VOUT VCCA 3.3V (Internal ) LDO 470k HPD_B (IEC) 11k LS_OE VCCA HPD_A CT_CP_HPD VCCA 3.3V (Internal) 10k 26k CEC_B (IEC) CEC_A 5VOUT SCL_B (IEC) VCCA 1.75k 10k ERC SCL_A 5VOUT VCCA 1.75k SDA_B (IEC) 10k ERC SDA_A LS_OE_INTERNAL PGND PGND GND ‘3.
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TPD12S015A SLLSE74C – JUNE 2011 – REVISED MARCH 2013 www.ti.com TERMINAL FUNCTIONS TERMINAL 6 TYPE DESCRIPTION NAME NO. 5VOUT F1 Power Out CEC_A B2 I/O System-side CEC bus I/O. This pin is bi-directional and referenced to VCCA. CEC_B D3 I/O HDMI-side CEC bus I/O. This pin is bi-directional and referenced to the 3.3-V internal supply.
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TPD12S015A www.ti.com SLLSE74C – JUNE 2011 – REVISED MARCH 2013 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN VCCA Supply voltage range VBAT Supply voltage range VI Input voltage range Voltage range applied to any output in the highimpedance or power-off state (2) VO MAX UNIT 4.0 V –0.3 6.0 HPD_B, Dx, CLKx –0.3 6.0 CT_CP_HPD, LS_OE –0.3 4.0 SCL_A, SDA_A, CEC_A, HPD_A –0.3 4.0 SCL_B, SDA_B, CEC_B –0.3 6.0 –0.3 VCCA + 0.
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TPD12S015A SLLSE74C – JUNE 2011 – REVISED MARCH 2013 www.ti.com ESD RATINGS PARAMETER PINS Human Body Model JESD22 A114-B SCL_A, SDA_A, CEC_A, CT_CP_HPD, LS_OE, VCCA Charged Device Model JESD22 C101 ALL IEC 61000-4-2 Contact Discharge D0+, D0-, D1+, D1-, D2+, D2-, CLK+, CLK-, SCL_B, SDA_B, CEC_B, HPD_B, 5VOUT, FB Human Body Model D0+, D0-, D1+, D1-, D2+, D2-, CLK+, CLK-, SCL_B, SDA_B, CEC_B, HPD_B, 5VOUT, FB TYP UNIT 2.
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TPD12S015A www.ti.com SLLSE74C – JUNE 2011 – REVISED MARCH 2013 DC-DC Converter (continued) PARAMETER TEST CONDITIONS Load transient response MIN VBAT = 3.6 V, IO = 5 to 65 mA, pulse of 10 µs, tr = tf = 0.1 µs IDD (idle) Power supply current from VBAT IO = 0 mA to DC/DC, enabled, unloaded IDD (disabled) Power supply current from VBAT, DC/DC Disabled, Unloaded TYP MAX 50 UNIT mVpk 30 50 µA VBAT = 2.3 V to 5.
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TPD12S015A SLLSE74C – JUNE 2011 – REVISED MARCH 2013 www.ti.com Voltage Level Shifter: CEC Lines (x_A/x_B Ports) TA = –40°C to 85°C unless otherwise specified PARAMETER TEST CONDITIONS VCCA MIN VCCA × 0.8 VOHA IOH = –10 μA, VI = VIH 1.1 V to 3.6 V VOLA IOL = 10 μA, VI = VIL 1.1 V to 3.6 V VOHB IOH = –10 μA, VI = VIH IOL = 3 mA, VI = VIL VOLB TYP VCCA × 0.17 V 0.4 1.1 V to 3.6 V 40 CEC_B (VT+ – VT–) 1.1 V to 3.
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TPD12S015A www.ti.com SLLSE74C – JUNE 2011 – REVISED MARCH 2013 I/O Capacitance (continued) TA = –40°C to 85°C unless otherwise specified PARAMETER CIO TEST CONDITIONS VCCA MIN TYP SCL_B, SDA_B VBAT = 0 V, Vbias = 2.5 V; AC input = 3.5 V(p-p); 0 V f = 100 kHz 20 CEC_B VBAT = 0 V, Vbias = 1.65 V; AC input = 2.5 V(pp); f = 100 kHz 20 0V VBAT = 3.3V, Vbias = 1.65 V; AC input = 2.5 V(p- 3.
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TPD12S015A SLLSE74C – JUNE 2011 – REVISED MARCH 2013 www.ti.com SWITCHING CHARACTERISTICS PARAMETER CL TEST CONDITIONS MIN TYP MAX UNIT Bus load capacitance (B side) 750 pF Bus load capacitance (A side) 15 Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 1.2V VCCA = 1.
PAGE 13
TPD12S015A www.ti.com SLLSE74C – JUNE 2011 – REVISED MARCH 2013 Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 1.5V (continued) VCCA = 1.
PAGE 14
TPD12S015A SLLSE74C – JUNE 2011 – REVISED MARCH 2013 www.ti.com Voltage Level Shifter: CEC Line (x_A & x_B ports); VCCA = 1.8V VCCA = 1.8 V tPLH PARAMETER PINS TEST CONDITIONS Propagation delay A to B CEC Channels Enabled MIN tf tr 13 B to A 0.
PAGE 15
TPD12S015A www.ti.com SLLSE74C – JUNE 2011 – REVISED MARCH 2013 Voltage Level Shifter: HPD Line (x_A & x_B ports); VCCA = 2.5V VCCA = 2.5 V tPLH PARAMETER PINS TEST CONDITIONS Propagation delay B to A CEC Channels Enabled tPLH MIN TYP MAX 10 B to A UNIT μs 9 tf A port fall time A Port CEC Channels Enabled 0.37 ns tr A port rise time A Port CEC Channels Enabled 0.39 ns Voltage Level Shifter: SCL, SDA Lines (x_A & x_B ports); VCCA = 3.3V VCCA = 3.
PAGE 16
TPD12S015A SLLSE74C – JUNE 2011 – REVISED MARCH 2013 www.ti.com APPLICATION INFORMATION DDC/CEC Level Shift Circuit Operation The TPD12S015A enables DDC translation from VCCA (system side) voltage levels to 5V (HDMI cable side) voltage levels without degradation of system performance. The TPD12S015A contains two bidirectional opendrain buffers specifically designed to support up-translation/down-translation between the low voltage, VCCA side DDC-bus and the 5V DDC-bus.
PAGE 17
TPD12S015A www.ti.com SLLSE74C – JUNE 2011 – REVISED MARCH 2013 Figure 3. DDC/CEC Level Shifter Operation (B to A Direction) Rise-Time Accelerators The HDMI cable side of the DDC lines incorporates rise-time accelerators to support the high capacitive load on the HDMI cable side. The rise time accelerator boosts the cable side DDC signal independent of which side of the bus is releasing the signal.
PAGE 18
TPD12S015A SLLSE74C – JUNE 2011 – REVISED MARCH 2013 www.ti.com Power-Save Mode The TPD12S015A integrates a power save mode to improve efficiency at light load. In power save mode the converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output voltage with several pulses and goes into power save mode once the output voltage exceeds the set threshold voltage.
PAGE 19
TPD12S015A www.ti.com SLLSE74C – JUNE 2011 – REVISED MARCH 2013 Parameter f is the switching frequency and ΔIL is the ripple current in the inductor, i.e., 20% x IL. With this calculated value and the calculated currents, it is possible to choose a suitable inductor. In typical applications a 1.0 μH inductance is recommended. The device has been optimized to operate with inductance values between 1.0 μH and 1.3 μH. It is recommended that an inductance value of at least 1.
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TPD12S015A SLLSE74C – JUNE 2011 – REVISED MARCH 2013 www.ti.com Table 1. Passive Components: Recommended Minimum Effective Values COMPONENT MIN TARGET MAX UNIT CIN 1.2 4.7 6.5 μF COUT 1.2 4.7 10 μF LIN 0.7 1 1.3 μH Figure 4. Board Layout (DC-DC Components) (Top View) List of components: • LIN = MURATA LQM21PN1R0MC0 (1.0 μH, 800 mA, 0805, Shielded) • CIN = COUT = MURATA LLL31MR70J475MA01 (4.7 μF, Low ESL type, 6.3 V, 0306, X7R) • CVCCA = MURATA GRM155R60J475ME87D (0.1 μF, 6.
PAGE 21
TPD12S015A www.ti.com SLLSE74C – JUNE 2011 – REVISED MARCH 2013 Top Segment Middle Segment Bottom Segment Figure 5. TPD12S015A EVM Top and Bottom View The EVM board has 6 layers.
PAGE 22
TPD12S015A SLLSE74C – JUNE 2011 – REVISED MARCH 2013 www.ti.com Figure 6. Layer 1: High-Speed Signal layer Figure 7.
PAGE 23
TPD12S015A www.ti.com SLLSE74C – JUNE 2011 – REVISED MARCH 2013 TYPICAL CHARACTERISTICS 75 5.5 65 ICCB Current (mA) 5.4 ICC_5VOUT 5VOUT 5.3 60 5.2 55 5.1 50 5.0 45 4.9 40 4.8 35 4.7 30 4.6 25 4.5 20 4.4 15 4.3 10 4.2 5 4.1 0 5VOUT Voltage (V) 70 4.0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Time (us) Figure 8. Load Transient Response 5.040 VBAT 5VOUT (20mA) 5VOUT (60mA) 4.1 VBAT Voltage (V) 4.0 5.020 5.000 3.9 4.980 3.8 4.960 3.7 4.940 3.6 4.
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TPD12S015A SLLSE74C – JUNE 2011 – REVISED MARCH 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 6.0 VCCA = VIH = 2.5 V, VBAT = 3.6 V 5.5 5.0 4.5 4.0 Voltage (V) 3.5 3.0 2.5 2.0 CT_CP_HPD 5VOUT (55 mA) 5VOUT(65 mA) 1.5 1.0 0.5 0.0 -0.5 -1.0 -50 0 50 100 150 200 250 300 Time (us) Figure 10. tSTART 6 VCCA = VIH = 2.5 V, VBAT = 3.6 V 5 CT_CP_HPD 5VOUT (55mA) 5VOUT (65mA) Voltage (V) 4 3 2 1 0 -1 0 500 1000 1500 2000 2500 3000 3500 4000 Time (us) Figure 11.
PAGE 25
TPD12S015A www.ti.com SLLSE74C – JUNE 2011 – REVISED MARCH 2013 TYPICAL CHARACTERISTICS (continued) 90 80 70 60 Amplitude (V) 50 40 30 20 10 0 -10 -20 -30 0 20 40 60 80 100 120 Time (ns) 140 160 180 200 Figure 12. IEC Clamping Waveforms 8 kV Contact (IEC ESD Pins) 30 20 10 0 Amplitude (V) -10 -20 -30 -40 -50 -60 -70 -80 -90 0 20 40 60 80 100 120 Time (ns) 140 160 180 200 Figure 13.
PAGE 26
TPD12S015A SLLSE74C – JUNE 2011 – REVISED MARCH 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 0 Closest signals D2+ to D2Farthest signals D2+ to CLK+ D2+ to D2D2+ to CLK+ -20 S21 (dB) -40 -60 -80 -100 Tested with typical operating voltage -120 1.00E+04 1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09 1.00E+10 Frequency (Hz) Figure 14. Channel-to-Channel Crosstalk 1.00000 S21 -1.00000 Insertion Loss (dB) -3.00000 -5.00000 -7.00000 -9.00000 -11.00000 -13.00000 -15.00000 1.
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TPD12S015A www.ti.com SLLSE74C – JUNE 2011 – REVISED MARCH 2013 0.65 100 0.60 90 0.55 80 0.50 70 0.45 60 0.40 50 0.35 40 0.30 30 0.25 20 015 I_5VOUT 0.20 Efficiency (%) Output Current (A) TYPICAL CHARACTERISTICS (continued) 10 015A Efficiency 0.15 0 2.3 2.8 3.3 3.8 4.3 4.8 5.3 VBAT (V) C001 Figure 16. Power Derating Curve Eye Diagram Without TPD12S015A (2.5 Gbps Data Rate) Eye Diagram With TPD12S015A (2.5 Gbps Data Rate) Figure 17.
PAGE 28
TPD12S015A SLLSE74C – JUNE 2011 – REVISED MARCH 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION VCCI VCCO DUT IN OUT Input CL PIN CL DDC, CEC (A side) 750 pF DDC, CEC, HPD (B side) 15 pF 1 MW VCC Input 50% 50% 0V Output 70% 30% 70% 30% tf VCC VOL tr A. RT termination resistance should be equal to ZOUT of pulse generators. B. CL includes probe and jig capacitance. C.
PAGE 29
TPD12S015A www.ti.com SLLSE74C – JUNE 2011 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision B (April 2012) to Revision C Page • Changed Board Layout section .......................................................................................................................................... 20 • Added Power Derating Curve .............................................................................................................................................
PAGE 30
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) TPD12S015AYFFR ACTIVE Package Type Package Pins Package Drawing Qty DSBGA YFF 28 3000 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) SNAGCU Level-1-260C-UNLIM (4) -40 to 85 PN015A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPD12S015AYFFR Package Package Pins Type Drawing SPQ DSBGA 3000 YFF 28 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 180.0 8.4 Pack Materials-Page 1 1.73 B0 (mm) K0 (mm) P1 (mm) 2.93 0.81 4.0 W Pin1 (mm) Quadrant 8.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPD12S015AYFFR DSBGA YFF 28 3000 182.0 182.0 17.
PAGE 33
D: Max = 2.79 mm, Min = 2.73 mm E: Max = 1.59 mm, Min = 1.
PAGE 34
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.