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TPIC6259

POWER LOGIC 8-BIT ADDRESSABLE LATCH

SLIS009A – APRIL 1992 – REVISED SEPTEMBER 1995

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

• Low r

DS(on)

. . . 1.3 Ω Typical

• Avalanche Energy ...75 mJ

• Eight Power DMOS Transistor Outputs of

250-mA Continuous Current

• 1.5-A Pulsed Current Per Output

• Output Clamp Voltage at 45 V

• Four Distinct Function Modes

• Low Power Consumption

description

This power logic 8-bit addressable latch controls

open-drain DMOS transistor outputs and is

designed for general-purpose storage applica-

tions in digital systems. Specific uses include

working registers, serial-holding registers, and

decoders or demultiplexers. This is a multi-

functional device capable of storing single-line

data in eight addressable latches with 3-to-8

decoding or demultiplexing mode active-low

DMOS outputs.

Four distinct modes of operation are selectable by

controlling the clear (CLR

) and enable (G) inputs

as enumerated in the function table. In the

addressable-latch mode, data at the data-in (D)

terminal is written into the addressed latch. The

addressed DMOS transistor output inverts the

data input with all unaddressed DMOS-transistor

outputs remaining in their previous states. In the

memory mode, all DMOS-transistor outputs

remain in their previous states and are unaffected

by the data or address inputs. To eliminate the

possibility of entering erroneous data in the latch,

enable G

should be held high (inactive) while the

address lines are changing. In the 3-to-8 decoding

or demultiplexing mode, the addressed output is inverted with respect to the D input and all other outputs are

high. In the clear mode, all outputs are high and unaffected by the address and data inputs.

Separate power and logic level ground pins are provided to facilitate maximum system flexibility. Pins 1, 10, 11,

and 20 are internally connected, and each pin must be externally connected to the power system ground in order

to minimize parasitic inductance. A single-point connection between pin 9, logic ground (LGND), and pins 1, 10,

11, and 20, power ground (PGND) must be externally made in a manner that reduces crosstalk between the

logic and load circuits.

The TPIC6259 is characterized for operation over the operating case temperature range of –40°C to 125°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PGND

DRAIN0

DRAIN1

DRAIN2

DRAIN3

LGND

PGND

CLR

DRAIN7

DRAIN6

DRAIN5

DRAIN4

PGND

DW OR N PACKAGE

(TOP VIEW)

OUTPUT OF

ADDRESSED

DRAIN

EACH

OTHER

DRAIN

INPUTS

FUNCTION

CLR G

FUNCTION TABLE

LATCH SELECTION TABLE

SELECT INPUTS DRAIN

ADDRESSED

H H X Memory

8-Line

Demultiplexer

LHX H H Clear

Addressable

Latch

S2 S1 S0

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Summary of content (16 pages)

PAGE 1
TPIC6259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS009A – APRIL 1992 – REVISED SEPTEMBER 1995 • • • • • • • Low rDS(on) . . . 1.3 Ω Typical Avalanche Energy . . . 75 mJ Eight Power DMOS Transistor Outputs of 250-mA Continuous Current 1.
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TPIC6259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS009A – APRIL 1992 – REVISED SEPTEMBER 1995 logic symbol† S0 S1 S2 G D CLR 3 0 8 12 13 18 19 8M 0/7 2 G8 Z9 Z10 9,0D 4 DRAIN0 10,0R 9,1D 5 DRAIN1 10,1R 9,2D 6 DRAIN2 10,2R 9,3D 7 DRAIN3 10,3R 9,4D 14 DRAIN4 10,4R 9,5D 15 DRAIN5 10,5R 9,6D 16 DRAIN6 10,6R 9,7D 17 10,7R † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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TPIC6259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS009A – APRIL 1992 – REVISED SEPTEMBER 1995 logic diagram (positive logic) 4 DRAIN0 S0 3 D C1 CLR 5 DRAIN1 D C1 CLR 6 DRAIN2 D S1 C1 8 CLR 7 DRAIN3 D C1 CLR S2 14 12 DRAIN4 D C1 CLR 15 DRAIN5 D C1 CLR 16 DRAIN6 D C1 CLR D 18 17 DRAIN7 D G CLR C1 13 CLR 1,10,11, 20 19 PGND • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 3
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TPIC6259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS009A – APRIL 1992 – REVISED SEPTEMBER 1995 schematic of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS VCC DRAIN 45 V Input 25 V 12 V 12 V LGND PGND LGND absolute maximum ratings over the recommended operating case temperature range (unless otherwise noted)† Logic supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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TPIC6259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS009A – APRIL 1992 – REVISED SEPTEMBER 1995 recommended operating conditions over recommended operating temperature range (unless otherwise noted) Logic supply voltage, VCC High-level input voltage, VIH MIN MAX 4.5 5.5 UNIT V 0.85 VCC Low-level input voltage, VIL V 0.15 VCC Pulsed drain output current, TC = 25°C, VCC = 5 V (see Notes 3 and 5) – 1.8 Setup time, D high before G↑, tsu (see Figure 2) 1.
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TPIC6259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS009A – APRIL 1992 – REVISED SEPTEMBER 1995 PARAMETER MEASUREMENT INFORMATION 5V CLR 0V 5V S0 5V 24 V 0V 5V 2 3 8 S1 ID VCC S0 0V RL = 95 Ω S1 12 Word S2 DUT Generator 4 –7, 13 (see Note A) G 14 –17 19 DRAIN CLR 18 D LGND PGND 9 1, 10, 11, 20 5V S2 Output 0V 5V G 0V 5V CL = 30 pF (see Note B) D 0V 24 V TEST CIRCUIT DRAIN5 0.5 V 24 V DRAIN3 0.5 V VOLTAGE WAVEFORMS Figure 1.
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TPIC6259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS009A – APRIL 1992 – REVISED SEPTEMBER 1995 PARAMETER MEASUREMENT INFORMATION TP K DRAIN 0.25 A 2500 µF 250 V Circuit Under Test dl/dt = 20 A/µs + 25 V L = 1 mH IF (see Note B) IF – 0 TP A 25% of IRM t2 t1 t3 Driver IRM RG VGG (see Note A) ta 50 Ω trr TEST CIRCUIT CURRENT WAVEFORM NOTES: A. The VGG amplitude and RG are adjusted for di/dt = 20 A/µs. A VGG double-pulse train is used to set IF = 0.
PAGE 8
TPIC6259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS009A – APRIL 1992 – REVISED SEPTEMBER 1995 TYPICAL CHARACTERISTICS MAXIMUM CONTINUOUS DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY PEAK AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE 800 10 I D – Maximum Continuous Drain Current of Each Output – mA IAS – Peak Avalanche Current – A TJS = 25°C 4 2 1 0.4 0.2 0.1 0.1 0.2 0.
PAGE 9
TPIC6259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS009A – APRIL 1992 – REVISED SEPTEMBER 1995 TYPICAL CHARACTERISTICS STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs LOGIC SUPPLY VOLTAGE r DS(on) – Static Drain-Source On-State Resistance – Ω r DS(on) – Static Drain-Source On-State Resistance – Ω STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 4 3.5 VCC = 5 V See Note A 3 TC = 125°C 2.5 2 TC = 25°C 1.5 1 TC = – 40°C 0.5 0 0.25 0.5 0.75 1 1.25 1.5 3 ID = 250 mA See Note A TC = 125°C 2.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 4-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPIC6259DWR Package Package Pins Type Drawing SOIC DW 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.8 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.3 2.7 12.0 24.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 4-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPIC6259DWR SOIC DW 20 2000 367.0 367.0 45.
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