Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Latch Transparent D latch Standard PDIP 20

TPIC6273

POWER LOGIC OCTAL D-TYPE LATCH

SLIS011A – APRIL 1992 – REVISED OCTOBER 1995

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

• Low r

DS(on)

. . . 1.3 Ω Typ

• Avalanche Energy . . . 75 mJ

• Eight Power DMOS Transistor Outputs of

250-mA Continuous Current

• 1.5-A Pulsed Current Per Output

• Output Clamp Voltage up to 45 V

• Low Power Consumption

description

The TPIC6273 is a monolithic high-voltage

high-current power logic octal D-type latch with

DMOS transistor outputs designed for use in

systems that require relatively high load power.

The device contains a built-in voltage clamp on the

outputs for inductive transient protection. Power

driver applications include relays, solenoids, and

other medium-current or high-voltage loads.

The TPIC6273 contains eight positive-edge-

triggered D-type flip-flops with a direct clear input.

Each flip-flop features an open-drain power

DMOS transistor output.

When clear (CLR

) is high, information at the D

inputs meeting the setup time requirements is

transferred to the DRAIN outputs on the positive-

going edge of the clock pulse. Clock triggering

occurs at a particular voltage level and is not

directly related to the transition time of the

positive-going pulse. When the clock input (CLK)

is at either the high or low level, the D input signal

has no effect at the output. An asynchronous CLR

is provided to turn all eight DMOS-transistor

outputs off.

The TPIC6273 is characterized for operation over

the operating case temperature range of –40°C

to 125°C.

DRAIN1

DRAIN2

DRAIN3

DRAIN4

DRAIN5

DRAIN6

DRAIN7

DRAIN8

CLR

DRAIN1

DRAIN2

DRAIN3

DRAIN4

GND

DRAIN8

DRAIN7

DRAIN6

DRAIN5

CLK

DW OR N PACKAGE

(TOP VIEW)

logic symbol

†

CLK

CLR

†

This symbol is in accordance with ANSI/IEEE Standard 91-1984

and IEC Publication 617-12.

INPUTS

OUTPUT

FUNCTION TABLE

(each channel)

CLK D

↑

Latched

CLR

DRAIN

H = high level, L = low level, X = irrelevant

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Summary of content (15 pages)

PAGE 1
TPIC6273 POWER LOGIC OCTAL D-TYPE LATCH SLIS011A – APRIL 1992 – REVISED OCTOBER 1995 • • • • • • Low rDS(on) . . . 1.3 Ω Typ Avalanche Energy . . . 75 mJ Eight Power DMOS Transistor Outputs of 250-mA Continuous Current 1.
PAGE 2
TPIC6273 POWER LOGIC OCTAL D-TYPE LATCH SLIS011A – APRIL 1992 – REVISED OCTOBER 1995 logic diagram (positive logic) 4 CLR D1 CLK 1 2 DRAIN1 R 1D 11 C1 5 DRAIN2 R D2 3 1D C1 6 DRAIN3 R D3 8 1D C1 7 DRAIN4 R D4 9 1D C1 14 DRAIN5 R D5 12 1D C1 15 DRAIN6 R D6 13 1D C1 16 DRAIN7 R D7 18 1D C1 17 DRAIN8 R D8 19 1D 10 C1 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GND
PAGE 3
TPIC6273 POWER LOGIC OCTAL D-TYPE LATCH SLIS011A – APRIL 1992 – REVISED OCTOBER 1995 schematic of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS VCC DRAIN 45 V Input 25 V 12 V 12 V GND GND absolute maximum ratings over recommended operating case temperature range (unless otherwise noted)† Logic supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Logic input voltage range, VI . . . .
PAGE 4
TPIC6273 POWER LOGIC OCTAL D-TYPE LATCH SLIS011A – APRIL 1992 – REVISED OCTOBER 1995 recommended operating conditions over recommended operating temperature range (unless otherwise noted) Logic supply voltage, VCC High-level input voltage, VIH MIN MAX 4.5 5.5 UNIT V 0.85 VCC Low-level input voltage, VIL V 0.15 VCC Pulsed drain output current, TC = 25°C, VCC = 5 V (see Notes 3 and 5) – 1.8 1.
PAGE 5
TPIC6273 POWER LOGIC OCTAL D-TYPE LATCH SLIS011A – APRIL 1992 – REVISED OCTOBER 1995 PARAMETER MEASUREMENT INFORMATION 5V 20 24 V 5V VCC 11 Word Generator (see Note A) CLK ID 0V RL = 95 Ω DUT CLK DRAIN 4 –7, 14 –17 5V D Output 0V D 1 5V CL = 30 pF (see Note B) CLR CLR 0V GND 24 V 10 Output 0.5 V TEST CIRCUIT VOLTAGE WAVEFORMS Figure 1.
PAGE 6
TPIC6273 POWER LOGIC OCTAL D-TYPE LATCH SLIS011A – APRIL 1992 – REVISED OCTOBER 1995 PARAMETER MEASUREMENT INFORMATION TP K DRAIN 0.25 A 2500 µF 250 V Circuit Under Test di/dt = 20 A/µs + 25 V L = 1 mH IF (see Note B) IF – 0 TP A 25% of IRM t2 t1 t3 Driver IRM RG VGG (see Note A) ta 50 Ω trr CURRENT WAVEFORM TEST CIRCUIT NOTES: A. The VGG amplitude and RG are adjusted for di/dt = 20 A/µs. A VGG double-pulse train is used to set IF = 0.25 A, where t1 = 10 µs, t2 = 7 µs, and t3 = 3 µs. B.
PAGE 7
TPIC6273 POWER LOGIC OCTAL D-TYPE LATCH SLIS011A – APRIL 1992 – REVISED OCTOBER 1995 TYPICAL CHARACTERISTICS MAXIMUM CONTINUOUS DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY PEAK AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE 10 800 I D – Maximum Continuous Drain Current of Each Output – mA 4 2 1 0.4 0.2 0.1 0.1 0.2 0.
PAGE 8
TPIC6273 POWER LOGIC OCTAL D-TYPE LATCH SLIS011A – APRIL 1992 – REVISED OCTOBER 1995 TYPICAL CHARACTERISTICS STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs LOGIC SUPPLY VOLTAGE r DS(on) – Static Drain-Source On-State Resistance – Ω r DS(on) – Static Drain-Source On-State Resistance – Ω STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 4 3.5 VCC = 5 V See Note A 3 TC = 125 °C 2.5 2 TC = 25 °C 1.5 1 TC = – 40 °C 0.5 0 0.25 0.5 0.75 1 1.25 1.5 3 2.5 2 TC = 25 °C 1.5 1 TC = – 40 °C 0.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 4-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPIC6273DWR Package Package Pins Type Drawing SOIC DW 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.8 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.3 2.7 12.0 24.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 4-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPIC6273DWR SOIC DW 20 2000 367.0 367.0 45.
PAGE 12
PAGE 13
PAGE 14
PAGE 15
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.