Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Shift register Shift register Open drain PDIP 20



    

SLIS010B − APRIL 1992 − REVISED MAY 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Low r

DS(on)

. . . 1.3 Ω Typical

D Avalanche Energy . . . 75 mJ

D Eight Power DMOS Transistor Outputs of

250-mA Continuous Current

D 1.5-A Pulsed Current Per Output

D Output Clamp Voltage at 45 V

D Devices Are Cascadable

D Low Power Consumption

description

The TPIC6595 is a monolithic, high-voltage, high-

current power 8-bit shift register designed for use

in systems that require relatively high load power.

The device contains a built-in voltage clamp on

the outputs for inductive transient protection.

Power driver applications include relays, sole-

noids, and other medium-current or high-voltage

loads.

This device contains an 8-bit serial-in, parallel-out

shift register that feeds an 8-bit D-type storage

storage registers on the rising edge of the

shift-register clock (SRCK) and the register clock

(RCK) respectively. The storage register transfers

data to the output buffer when shift-

) is high. When SRCLR is

low, the input shift register is cleared. When output

enable (G

) is held high, all data in the output

buffers is held low and all drain outputs are off.

When G

is held low, data from the storage register

is transparent to the output buffers. The serial

output (SER OUT) allows for cascading of the

data from the shift register to additional devices.

Outputs are low-side, open-drain DMOS

transistors with output ratings of 45 V and 250-mA

continuous sink current capability. When data in the output buffers is low, the DMOS-transistor outputs are off.

When data is high, the DMOS-transistor outputs have sink current capability.

Separate power and logic level ground pins are provided to facilitate maximum system flexibility. Pins 1, 10, 11,

and 20 are internally connected, and each pin must be externally connected to the power system ground in order

to minimize parasitic inductance. A single-point connection between pin 19, logic ground (LGND), and pins 1,

10, 11, and 20, power grounds (PGND), must be externally made in a manner that reduces crosstalk between

the logic and load circuits.

The TPIC6595 is characterized for operation over the operating case temperature range of −40°C to 125°C.

   ! "#$ !  %#&'" ($)

(#"! "  !%$""! %$ *$ $!  $+! !#$!

!(( ,-) (#" %"$!!. ($!  $"$!!'- "'#($

$!.  '' %$$!)

†

This symbol is in accordance with ANSI/IEEE Std 91-1984

and IEC Publication 617-12.

PGND

SER IN

DRAIN0

DRAIN1

DRAIN2

DRAIN3

SRCLR

PGND

LGND

SER OUT

DRAIN7

DRAIN6

DRAIN5

DRAIN4

SRCK

RCK

PGND

DW OR N PACKAGE

(TOP VIEW)

logic symbol

†

SRG8

EN3

RCK

SRCLR

SRCK

SER IN

DRAIN0

DRAIN1

DRAIN2

DRAIN3

DRAIN4

DRAIN5

DRAIN6

DRAIN7

SER OUT

Summary of content (16 pages)

PAGE 1
SLIS010B − APRIL 1992 − REVISED MAY 2005 D Low rDS(on) . . . 1.3 Ω Typical D Avalanche Energy . . . 75 mJ D Eight Power DMOS Transistor Outputs of D D D D DW OR N PACKAGE (TOP VIEW) PGND VCC SER IN DRAIN0 DRAIN1 DRAIN2 DRAIN3 SRCLR G PGND 250-mA Continuous Current 1.
PAGE 2
SLIS010B − APRIL 1992 − REVISED MAY 2005 logic diagram (positive logic) G RCK SRCLR 9 12 4 8 D SRCK 13 D C2 C1 CLR SER IN 5 3 D DRAIN1 D C2 C1 CLR 6 D DRAIN2 D C2 C1 7 CLR DRAIN3 D D C1 C2 CLR 14 D DRAIN4 D C2 C1 CLR 15 D DRAIN5 D C2 C1 16 CLR DRAIN6 D C2 D C1 17 CLR D DRAIN7 D C2 C1 CLR 1, 10, 11, 20 18 2 DRAIN0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SER OUT PGND
PAGE 3
SLIS010B − APRIL 1992 − REVISED MAY 2005 schematic of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS VCC DRAIN 45 V Input 25 V 12 V 12 V PGND LGND LGND absolute maximum ratings over recommended operating case temperature range (unless otherwise noted)† Logic supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Logic input voltage range, VI . .
PAGE 4
SLIS010B − APRIL 1992 − REVISED MAY 2005 recommended operating conditions over recommended operating temperature range (unless otherwise noted) Logic supply voltage, VCC High-level input voltage, VIH MIN MAX 4.5 5.5 UNIT V 0.85 VCC Low-level input voltage, VIL V 0.15 VCC Pulsed drain output current, TC = 25°C, VCC = 5 V (see Notes 3 and 5) −1.8 1.
PAGE 5
SLIS010B − APRIL 1992 − REVISED MAY 2005 thermal resistance PARAMETER TEST CONDITIONS MIN DW package RθJA JA Thermal resistance, junction-to-ambient MAX UNIT 111 All 8 outputs with equal power N package °C/W 108 PARAMETER MEASUREMENT INFORMATION 24 V 5V 7 2 8 SRCLR 12 9 DRAIN SER IN 4 3 2 1 0 5V 0V 5V RL = 95 Ω DUT 3 5 ID VCC 13 SRCK Word Generator (see Note A) 6 SRCK 4 −7, 14 −17 G Output SER IN CL = 30 pF (see Note B) RCK 0V 5V 0V
PAGE 6
SLIS010B − APRIL 1992 − REVISED MAY 2005 PARAMETER MEASUREMENT INFORMATION TP K DRAIN Circuit Under Test 0.25 A 2500 µF 250 V di/dt = 20 A/µs + 25 V L = 1 mH IF (see Note B) IF − 0 TP A 25% of IRM t2 t1 t3 Driver IRM RG VGG (see Note A) ta 50 Ω trr CURRENT WAVEFORM TEST CIRCUIT NOTES: A. The VGG amplitude and RG are adjusted for di/dt = 20 A/µs. A VGG double-pulse train is used to set IF = 0.25 A, where t1 = 10 µs, t2 = 7 µs, and t3 = 3 µs. B.
PAGE 7
SLIS010B − APRIL 1992 − REVISED MAY 2005 TYPICAL CHARACTERISTICS PEAK AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE SUPPLY CURRENT vs FREQUENCY 10 3.5 3 4 I CC − Supply Current − mA IAS − Peak Avalanche Current − A TJS = 25°C 2 1 0.4 0.2 VCC = 5 V TJS = − 40°C to 125°C 2.5 2 1.5 1 0.5 0.1 0.1 0.2 0.4 1 2 4 0 0.
PAGE 8
SLIS010B − APRIL 1992 − REVISED MAY 2005 TYPICAL CHARACTERISTICS STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs LOGIC SUPPLY VOLTAGE r DS(on) − Static Drain-Source On-State Resistance − Ω rDS(on) − Static Drain-Source On-State Resistance − Ω STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 4 3.5 VCC = 5 V See Note A 3 TC = 125°C 2.5 2 TC = 25°C 1.5 1 TC = − 40°C 0.5 0 0.25 0.5 0.75 1 1.25 1.5 3 2.5 2 TC = 25°C 1.5 1 TC = − 40°C 0.
PAGE 9
SLIS010B − APRIL 1992 − REVISED MAY 2005 Revision History DATE REV PAGE 5/18/05 B 5 10/1/96 A 4/1992 * SECTION DESCRIPTION Figure 1 Changed SRCLR timing diagram — — Original reversion NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 4-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPIC6595DWR Package Package Pins Type Drawing SOIC DW 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.8 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.3 2.7 12.0 24.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 4-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPIC6595DWR SOIC DW 20 2000 367.0 367.0 45.
PAGE 13
PAGE 14
PAGE 15
PAGE 16
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.