Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Shift register Shift register Open drain PDIP 20



    

SLIS094A − MARCH 2000 − REVISED MAY 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Low r

DS(on)

...1 Ω Typ

D Output Short-Circuit Protection

D Avalanche Energy . . . 75 mJ

D Eight 350-mA DMOS Outputs

D 50-V Switching Capability

D Enhanced Cascading for Multiple Stages

D All Registers Cleared With Single Input

D Low Power Consumption

description

The TPIC6A596 is a monolithic, high-voltage,

high-current power logic 8-bit shift register

designed for use in systems that require relatively

high load power. The device contains a built-in

voltage clamp on the outputs for inductive

transient protection. Power driver applications

include relays, solenoids, and other medium-

current or high-voltage loads. Each open-drain

DMOS transistor features an independent

chopping current-limiting circuit to prevent

damage in the case of a short circuit.

This device contains an 8-bit serial-in, parallel-out

shift register that feeds an 8-bit, D-type storage

storage registers on the rising edge of the shift-

(RCK), respectively. The storage register

transfers data to the output buffer when shift-

) is high. When SRCLR is low, all registers in the device are cleared. When output enable

is held high, all data in the output buffers is held low and all drain outputs are off. When G is held low, data

from the storage register is transparent to the output buffers. The serial output (SER OUT) is clocked out of the

device on the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide

improved performance for applications where clock signals may be skewed, devices are not located near one

another, or the system must tolerate electromagnetic interference.

Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and a 350-mA continuous sink

current capability. When data in the output buffers is low, the DMOS-transistor outputs are off. When data is high,

the DMOS-transistor outputs have sink current capability.

Separate power ground (PGND) and logic ground (LGND) terminals are provided to facilitate maximum system

flexibility. All PGND terminals are internally connected, and each PGND terminal must be externally connected

to the power system ground in order to minimize parasitic impedance. A single-point connection between LGND

and PGND must be made externally in a manner that reduces crosstalk between the logic and load circuits.

The TPIC6A596 is offered in a thermally-enhanced dual-in-line (NE) package and a wide-body surface-mount

(DW) package. The TPIC6A596 is characterized for operation over the operating case temperature range of

−40°C to 125°C.

   ! "#$ !  %#&'" ($)

(#"! "  !%$""! %$ *$ $!  $+! !#$!

!(( ,-) (#" %"$!!. ($!  $"$!!'- "'#($

$!.  '' %$$!)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DRAIN2

DRAIN3

SRCLR

PGND

RCK

SRCK

DRAIN4

DRAIN5

DRAIN1

DRAN0

SER IN

PGND

LGND

SER OUT

DRAIN7

DRAIN6

NE PACKAGE

(TOP VIEW)

DRAIN2

DRAIN3

SRCLR

PGND

RCK

SRCK

DRAIN4

DRAIN5

DRAIN1

DRAIN0

SER IN

PGND

LGND

SER OUT

DRAIN7

DRAIN6

DW PACKAGE

(TOP VIEW)

Summary of content (17 pages)

PAGE 1
SLIS094A − MARCH 2000 − REVISED MAY 2005 D D D D D D D D Low rDS(on) . . . 1 Ω Typ Output Short-Circuit Protection Avalanche Energy . . .
PAGE 2
SLIS094A − MARCH 2000 − REVISED MAY 2005 logic symbol† G EN3 RCK C2 SRCLR SRCK SER IN R SRG8 C1 1D 2 3 DRAIN0 DRAIN1 DRAIN2 DRAIN3 DRAIN4 DRAIN5 DRAIN6 2 3 DRAIN7 SER OUT † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
PAGE 3
SLIS094A − MARCH 2000 − REVISED MAY 2005 logic diagram (positive logic) G DRAIN0 RCK D SRCK C1 D C2 SRCLR CLR CLR D C1 D C2 CLR CLR D C1 D C2 CLR CLR D C1 D C2 CLR CLR C1 D C2 CLR CLR D D DRAIN1 DRAIN2 Current Limit and Charge Pump SER IN DRAIN3 DRAIN4 DRAIN5 C1 D C2 CLR CLR D C1 D C2 CLR CLR D C1 D C2 CLR CLR DRAIN6 DRAIN7 D PGND C1 CLR SER OUT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
PAGE 4
SLIS094A − MARCH 2000 − REVISED MAY 2005 schematic of inputs and outputs TYPICAL OF SERIAL OUT EQUIVALENT OF EACH INPUT VCC TYPICAL OF ALL DRAIN OUTPUTS DRAIN VCC Input SER OUT 25 V 12 V RSENSE LGND LGND PGND LGND absolute maximum ratings over recommended operating case temperature range (unless otherwise noted)† Logic supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
SLIS094A − MARCH 2000 − REVISED MAY 2005 recommended operating conditions MIN Logic supply voltage, VCC MAX 4.5 High-level input voltage, VIH 5.5 0.85 VCC Low-level input voltage, VIL 0 Pulsed drain output current, TC = 25°C, VCC = 5 V (see Notes 3 and 5) UNIT V VCC 0.15 VCC −1.8 0.
PAGE 6
SLIS094A − MARCH 2000 − REVISED MAY 2005 switching characteristics, VCC = 5 V, TC = 25°C PARAMETER TEST CONDITIONS tPHL tPLH Propagation delay time, high-to-low-level output from G tr tf Rise time, drain output Propagation delay time, low-to-high-level output from G MIN TYP CL = 30 pF, ID = 350 mA, See Figures 1, 2, and 12 tpd Propagation delay time, SRCK↓ to SEROUT f(SRCK) Serial clock frequency CL = 30 pF, See Note 8 ta trr Reverse-recovery-current rise
PAGE 7
SLIS094A − MARCH 2000 − REVISED MAY 2005 PARAMETER MEASUREMENT INFORMATION 5V G 50% 50% 0V tPLH Output 5V tPHL 90% 24 V 90% 10% 10% tr 24 V 0.
PAGE 8
SLIS094A − MARCH 2000 − REVISED MAY 2005 PARAMETER MEASUREMENT INFORMATION OUTPUT CURRENT vs TIME FOR INCREASING LOAD RESISTANCE REGION 1 CURRENT WAVEFORM 1.5 IOK IOK (see Notes A and B) I O − Output Current I O − Output Current − A 1.25 1 0.75 0.5 0 0.25 t1 t2 t1 t2 t1 t1 ≈ 40 µs t2 ≈ 2.5 ms 0 Region 2 Region 1 Time Time First output current pulses after turn-on in chopping mode with resistive load. NOTES: A.
PAGE 9
SLIS094A − MARCH 2000 − REVISED MAY 2005 PARAMETER MEASUREMENT INFORMATION TP K DRAIN Circuit Under Test 0.35 A 2500 µF 250 V di/dt = 20 A/µs + 24 V L = 1 mH IF (see Note B) IF − 0 TP A 25% of IRM t2 t1 t3 Driver IRM (see Note C) RG VGG (see Note A) ta 50 Ω trr CURRENT WAVEFORM TEST CIRCUIT NOTES: A. The VGG amplitude and RG are adjusted for di/dt = 20 A/µs. A VGG double-pulse train is used to set IF = 0.
PAGE 10
SLIS094A − MARCH 2000 − REVISED MAY 2005 TYPICAL CHARACTERISTICS MAXIMUM CONTINUOUS DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY SUPPLY CURRENT vs FREQUENCY 0.7 4 VCC = 5 V TJS = − 40°C to 125°C ID − Maximum Continuous Drain Current of Each Output − A I CC − Supply Current − mA 3.5 3 2.5 2 1.5 1 0.5 0 0.1 VCC = 5 V 0.6 TA = 25°C 0.5 0.4 TA = 100°C 0.3 0.2 TA = 125°C 0.
PAGE 11
SLIS094A − MARCH 2000 − REVISED MAY 2005 STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs LOGIC SUPPLY VOLTAGE SWITCHING TIME vs CASE TEMPERATURE 140 2 ID = 350 mA See Note A 1.75 120 TC = 125°C tPLH 1.5 Switching Time − ns r DS(on) − Static Drain-Source On-State Resistance − Ω TYPICAL CHARACTERISTICS 1.25 TC = 25°C 1 0.75 TC = − 40°C 100 80 tr 60 0.5 0.
PAGE 12
SLIS094A − MARCH 2000 − REVISED MAY 2005 THERMAL INFORMATION NE PACKAGE TRANSIENT THERMAL IMPEDANCE vs ON TIME The single-pulse curve represents measured data.
PAGE 13
PACKAGE OPTION ADDENDUM www.ti.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPIC6A596DWR Package Package Pins Type Drawing SOIC DW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.7 2.7 12.0 24.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPIC6A596DWR SOIC DW 24 2000 367.0 367.0 45.
PAGE 16
PAGE 17
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.