Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Latch D type, Addressable DMOS SOIC 20

TPIC6B259

POWER LOGIC 8-BIT ADDRESSABLE LATCH

SLIS030 – APRIL 1994 – REVISED JULY 1995

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Low r

DS(on)

...5 Ω Typical

Avalanche Energy ...30 mJ

Eight Power DMOS-Transistor Outputs of

150-mA Continuous Current

500-mA Typical Current-Limiting Capability

Output Clamp Voltage . . . 50 V

Four Distinct Function Modes

Low Power Consumption

description

This power logic 8-bit addressable latch controls

open-drain DMOS-transistor outputs and is

designed for general-purpose storage

applications in digital systems. Specific uses

include working registers, serial-holding registers,

and decoders or demultiplexers. This is a multi-

functional device capable of storing single-line

data in eight addressable latches and 3-to-8

decoder or demultiplexer with active-low DMOS

outputs.

Four distinct modes of operation are selectable by

controlling the clear (CLR

) and enable (G) inputs

as enumerated in the function table. In the

addressable-latch mode, data at the data-in (D)

terminal is written into the addressed latch. The

addressed DMOS-transistor output inverts the

data input with all unaddressed DMOS-transistor

outputs remaining in their previous states. In the

memory mode, all DMOS-transistor outputs

remain in their previous states and are unaffected

by the data or address inputs. To eliminate the

possibility of entering erroneous data in the latch,

enable G

should be held high (inactive) while the

address lines are changing. In the 3-to-8 decoding

or demultiplexing mode, the addressed output is

inverted with respect to the D input and all other

outputs are off. In the clear mode, all outputs are off and unaffected by the address and data inputs. When data

is low for a given output, the DMOS-transistor output is off. When data is high, the DMOS-transistor output has

sink-current capability.

Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and 150-mA continuous

sink-current capability. Each output provides a 500-mA typical current limit at T

= 25°C. The current limit

decreases as the junction temperature increases for additional device protection.

The TPIC6B259 is characterized for operation over the operating case temperature range of –40°C to 125°C.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

DRAIN0

DRAIN1

DRAIN2

DRAIN3

GND

CLR

DRAIN7

DRAIN6

DRAIN5

DRAIN4

GND

DW OR N PACKAGE

(TOP VIEW)

OUTPUT OF

ADDRESSED

DRAIN

EACH

OTHER

DRAIN

INPUTS

FUNCTION

CLR G

FUNCTION TABLE

LATCH SELECTION TABLE

SELECT INPUTS DRAIN

ADDRESSED

H H X Memory

8-Line

Demultiplexer

L H X H H Clear

Addressable

Latch

S2 S1 S0

NC – No internal connection

H = high level, L = low level

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Summary of content (17 pages)

PAGE 1
TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS030 – APRIL 1994 – REVISED JULY 1995 D D D D D D D Low rDS(on) . . . 5 Ω Typical Avalanche Energy . . . 30 mJ Eight Power DMOS-Transistor Outputs of 150-mA Continuous Current 500-mA Typical Current-Limiting Capability Output Clamp Voltage . . .
PAGE 2
TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS030 – APRIL 1994 – REVISED JULY 1995 logic symbol† S0 S1 S2 G D CLR 3 0 8 12 13 18 19 8M 0/7 2 G8 Z9 Z10 9,0D 4 DRAIN0 10,0R 9,1D 5 DRAIN1 10,1R 9,2D 6 DRAIN2 10,2R 9,3D 7 DRAIN3 10,3R 9,4D 14 DRAIN4 10,4R 9,5D 15 DRAIN5 10,5R 9,6D 16 DRAIN6 10,6R 9,7D 17 10,7R † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
PAGE 3
TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS030 – APRIL 1994 – REVISED JULY 1995 logic diagram (positive logic) 4 DRAIN0 S0 3 D C1 CLR 5 DRAIN1 D C1 CLR 6 DRAIN2 D S1 C1 CLR 8 7 DRAIN3 D C1 CLR S2 14 12 DRAIN4 D C1 CLR 15 DRAIN5 D C1 CLR 16 DRAIN6 D C1 CLR 18 17 D DRAIN7 D G CLR C1 CLR 13 9,10,11 19 GND POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
PAGE 4
TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS030 – APRIL 1994 – REVISED JULY 1995 schematic of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS VCC DRAIN 50 V Input 25 V 20 V 12 V GND GND absolute maximum ratings over the recommended operating case temperature range (unless otherwise noted)† Logic supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS030 – APRIL 1994 – REVISED JULY 1995 recommended operating conditions Logic supply voltage, VCC High-level input voltage, VIH MIN MAX 4.5 5.5 UNIT V 0.85 VCC Low-level input voltage, VIL Pulsed drain output current, TC = 25°C, VCC = 5 V (see Notes 3 and 5) V 0.
PAGE 6
TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS030 – APRIL 1994 – REVISED JULY 1995 thermal resistance PARAMETER RθJA TEST CONDITIONS DW package junction to ambient Thermal resistance junction-to-ambient All 8 outputs with equal power N package MIN MAX 90 95 UNIT °C/W PARAMETER MEASUREMENT INFORMATION 5V CLR 5V 0V 5V 24 V S0 2 3 8 Word Generator (see Note A) 12 13 19 18 S0 VCC 0V 5V ID S2 DUT G 4 –7, 14 –17 0V 5V Output S2 0V DRAIN CLR D S1 RL = 235 Ω S1 GND CL = 30 pF (se
PAGE 7
TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS030 – APRIL 1994 – REVISED JULY 1995 PARAMETER MEASUREMENT INFORMATION 5V G 5V 2 Word Generator (see Note A) 18 24 V 19 VCC D 50% tPLH ID D G DRAIN 4 –7, 14 –17 24 V 90% 10% 10% tr Output 0.5 V tf SWITCHING TIMES GND CL = 30 pF (see Note B) 9, 10,11 tPHL 90% Output 235 Ω 13 50% 0V CLR DUT Word Generator (see Note A) 0V 5V 5V G 50% 0V tsu th TEST CIRCUIT 5V D 50% 50% 0V tw INPUT SETUP AND HOLD WAVEFORMS NOTES: A.
PAGE 8
TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS030 – APRIL 1994 – REVISED JULY 1995 PARAMETER MEASUREMENT INFORMATION 5V 15 V tw 2 12 S2 8 Word Generator (see Note A) VCC S0 13 Input See Note B ID DUT G 18 5V 10.5 Ω S1 3 D DRAIN 19 4 –7, 14 –17 tav 0V IAS = 0.5 A 200 mH ID VDS CLR V(BR)DSX = 50 V MIN VDS GND 9, 10, 11 VOLTAGE AND CURRENT WAVEFORMS TEST CIRCUIT NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω . B.
PAGE 9
TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS030 – APRIL 1994 – REVISED JULY 1995 TYPICAL CHARACTERISTICS 8 SWITCHING TIME vs CASE TEMPERATURE 300 ID = 100 mA See Note A 7 ID = 100 mA See Note A tf TC = 125°C 250 6 Switching Time – ns r DS(on) – Static Drain-to-Source On-State Resistance – Ω STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs LOGIC SUPPLY VOLTAGE 5 TC = 25°C 4 3 TC = – 40°C 2 tr 200 tPLH 150 tPHL 100 1 0 4 4.5 5 5.5 6 6.
PAGE 10
TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS030 – APRIL 1994 – REVISED JULY 1995 MAXIMUM CONTINUOUS DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY I D – Maximum Continuous Drain Current of Each Output – A 0.45 VCC = 5 V 0.4 0.35 0.3 0.25 TC = 25°C 0.2 0.15 TC = 100°C 0.1 TC = 125°C 0.
PAGE 11
PACKAGE OPTION ADDENDUM www.ti.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 4-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPIC6B259DWR Package Package Pins Type Drawing SOIC DW 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.8 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.3 2.7 12.0 24.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 4-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPIC6B259DWR SOIC DW 20 2000 367.0 367.0 45.
PAGE 14
PAGE 15
PAGE 16
PAGE 17
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.