Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Shift register Shift register Open drain TSSOP 16



    

SLIS061C − JULY 1998 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Low r

DS(on)

...7 Ω Typ

D Avalanche Energy . . . 30 mJ

D Eight Power DMOS Transistor Outputs of

100-mA Continuous Current

D 250-mA Current Limit Capability

D ESD Protection . . . 2500 V

D Output Clamp Voltage ...33 V

D Devices Are Cascadable

D Low Power Consumption

description

The TPIC6C595 is a monolithic, medium-voltage,

low-current power 8-bit shift register designed for

use in systems that require relatively moderate

load power such as LEDs. The device contains a

built-in voltage clamp on the outputs for inductive

transient protection. Power driver applications

include relays, solenoids, and other low-current or

medium-voltage loads.

This device contains an 8-bit serial-in, parallel-out

shift register that feeds an 8-bit D-type storage

storage registers on the rising edge of the shift

(RCK), respectively. The device transfers data out

the serial output (SER OUT) port on the rising

edge of SRCK. The storage register transfers data

to the output buffer when shift register clear (CLR

)

is high. When CLR

is low, the input shift register is

cleared. When output enable (G

) is held high, all

data in the output buffers is held low and all drain

outputs are off. When G

is held low, data from the storage register is transparent to the output buffers. When

data in the output buffers is low, the DMOS transistor outputs are off. When data is high, the DMOS transistor

outputs have sink-current capability. The SER OUT allows for cascading of the data from the shift register to

additional devices.

This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These

circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,

Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated

voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device

should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,

preferably either V

or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for

Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

logic symbol

†

SRG8

†

This symbol is in accordance with ANSI/IEEE Std 91-1984

and IEC Publication 617-12.

EN3

RCK

CLR

SRCK

SER IN

DRAIN0

DRAIN1

DRAIN2

DRAIN3

DRAIN4

DRAIN5

DRAIN6

DRAIN7

SER OUT

SER IN

DRAIN0

DRAIN1

DRAIN2

DRAIN3

CLR

GND

SRCK

DRAIN7

DRAIN6

DRAIN5

DRAIN4

RCK

SER OUT

D, N, OR PW PACKAGE

(TOP VIEW)

   ! "#$ !  %#&'" ($)

(#"! "  !%$""! %$ *$ $!  $+! !#$!

!(( ,-) (#" %"$!!. ($!  $"$!!'- "'#($

$!.  '' %$$!)

Summary of content (20 pages)

PAGE 1
SLIS061C − JULY 1998 − REVISED APRIL 2005 D Low rDS(on) . . . 7 Ω Typ D Avalanche Energy . . . 30 mJ D Eight Power DMOS Transistor Outputs of D D D D D D, N, OR PW PACKAGE (TOP VIEW) VCC SER IN DRAIN0 DRAIN1 DRAIN2 DRAIN3 CLR G 100-mA Continuous Current 250-mA Current Limit Capability ESD Protection . . . 2500 V Output Clamp Voltage . . .
PAGE 2
SLIS061C − JULY 1998 − REVISED APRIL 2005 description (continued) Outputs are low-side, open-drain DMOS transistors with output ratings of 33 V and 100 mA continuous sink-current capability. Each output provides a 250-mA maximum current limit at TC = 25°C. The current limit decreases as the junction temperature increases for additional device protection.
PAGE 3
SLIS061C − JULY 1998 − REVISED APRIL 2005 schematic of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS VCC DRAIN 33 V Input 25 V 20 V 12 V GND GND absolute maximum ratings over recommended operating case temperature range (unless otherwise noted)† Logic supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Logic input voltage range, VI . . . . . .
PAGE 4
SLIS061C − JULY 1998 − REVISED APRIL 2005 recommended operating conditions Logic supply voltage, VCC High-level input voltage, VIH MIN MAX UNIT 4.5 5.5 V 0.85 VCC Low-level input voltage, VIL V 0.
PAGE 5
SLIS061C − JULY 1998 − REVISED APRIL 2005 switching characteristics, VCC = 5 V, TC = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH tPHL Propagation delay time, low-to-high-level output from G 80 ns Propagation delay time, high-to-low-level output from G 50 ns tpd Propagation delay time, SRCK to SEROUT 20 ns tr tf Rise time, drain output 100 ns Fall time, drain output 80 ns ta trr Reverse-recovery-current rise time CL = 30 pF, ID = 75 mA,
PAGE 6
SLIS061C − JULY 1998 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION 5V G 5V 50% 50% 0V 15 V tPLH tPHL 1 7 15 Word Generator (see Note A) 2 10 8 VCC CLR SRCK Output ID RL = 200 Ω 3 −6, 11 −14 DUT 24 V 90% 10% 10% tr Output 0.5 V tf SWITCHING TIMES DRAIN SER IN CL = 30 pF (see Note B) RCK G 90% GND 5V 50% SRCK 0V tsu 16 th 5V TEST CIRCUIT SER IN 50% 50% 0V tw INPUT SETUP AND HOLD WAVEFORMS NOTES: A.
PAGE 7
SLIS061C − JULY 1998 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION 5V 15 V tw 1 7 CLR VCC 30 Ω Word Generator (see Note A) 2 10 8 DUT See Note B 1.5 H SER IN 3 −6, 11 −14 0V IAS = 200 mA ID VDS DRAIN RCK G 5V Input ID 15 SRCK tav GND V(BR)DSX = 33 V MIN VDS 16 VOLTAGE AND CURRENT WAVEFORMS SINGLE-PULSE AVALANCHE ENERGY TEST CIRCUIT NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω. B.
PAGE 8
SLIS061C − JULY 1998 − REVISED APRIL 2005 TYPICAL CHARACTERISTICS 30 VCC = 5 V See Note A 25 TC = 125°C 20 15 10 TC = 25°C 5 TC = − 40°C 0 50 70 90 110 130 150 170 190 210 250 STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs LOGIC SUPPLY VOLTAGE rDS(on) − Static Drain-to-Source On-State Resistance − Ω rDS(on) − Drain-to-Source On-State Resistance − Ω DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT 12 10 8 TC = 25°C 6 4 TC = − 40°C 2 0 4.0 4.
PAGE 9
SLIS061C − JULY 1998 − REVISED APRIL 2005 MAXIMUM CONTINUOUS DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY MAXIMUM PEAK DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY 0.25 VCC = 5 V 0.20 0.15 TC = 25°C 0.10 TC = 100°C TC = 125°C 0.05 0.00 1 2 3 4 5 6 7 8 ID − Maximum Peak Drain Current of Each Output − A ID − Maximum Continuous Drain Current of Each Output − A THERMAL INFORMATION 0.
PAGE 10
SLIS061C − JULY 1998 − REVISED APRIL 2005 THERMAL INFORMATION D PACKAGE† NORMALIZED JUNCTION - TO -AMBIENT THERMAL RESISTANCE vs PULSE DURATION RθJA − Normalized Junction-to-Ambient Thermal Resistance − °C/W 10 DC Conditions 1 d = 0.5 d = 0.2 d = 0.1 0.1 d = 0.05 d = 0.02 d = 0.01 0.01 Single Pulse 0.001 tc tw ID 0 0.0001 0.0001 0.001 0.01 0.
PAGE 11
PACKAGE OPTION ADDENDUM www.ti.
PAGE 12
PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Only one of markings shown within the brackets will appear on the physical device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPIC6C595DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TPIC6C595DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TPIC6C595DRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPIC6C595DR SOIC D 16 2500 367.0 367.0 38.0 TPIC6C595DR SOIC D 16 2500 367.0 367.0 38.0 TPIC6C595DRG4 SOIC D 16 2500 367.0 367.0 38.0 TPIC6C595PWR TSSOP PW 16 2000 367.0 367.0 35.0 TPIC6C595PWRG4 TSSOP PW 16 2000 367.0 367.0 35.
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 19
PAGE 20
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.