Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Shift register Shift register Open drain SOIC 16 N



    

SLIS093C − MARCH 2000 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Low r

DS(on)

...7 Ω Typ

D Avalanche Energy . . . 30 mJ

D Eight Power DMOS Transistor Outputs of

100-mA Continuous Current

D 250-mA Current Limit Capability

D ESD Protection . . . 2500 V

D Output Clamp Voltage ...33 V

D Enhanced Cascading for Multiple Stages

D All Registers Cleared With Single Input

D Low Power Consumption

description

The TPIC6C596 is a monolithic, medium-voltage,

low-current power 8-bit shift register designed for

use in systems that require relatively moderate

load power such as LEDs. The device contains a

built-in voltage clamp on the outputs for inductive

transient protection. Power driver applications

include relays, solenoids, and other low-current or

medium-voltage loads.

This device contains an 8-bit serial-in, parallel-out

shift register that feeds an 8-bit D-type storage

storage registers on the rising edge of the shift

(RCK), respectively. The storage register trans-

fers data to the output buffer when shift register

clear (CLR

) is high. When CLR is low, all registers

in the device are cleared. When output enable (G

)

is held high, all data in the output buffers is held

low and all drain outputs are off. When G

is held

low, data from the storage register is transparent to the output buffers. When data in the output buffers is low,

the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs have sink-current

capability. The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide

additional hold time for cascaded applications. This will provide improved performance for applications where

clock signals may be skewed, devices are not located near one another, or the system must tolerate

electromagnetic interference.

This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These

circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,

Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated

voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device

should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,

preferably either V

or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for

Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

logic symbol

†

SRG8

†

This symbol is in accordance with ANSI/IEEE Std 91-1984

and IEC Publication 617-12.

EN3

RCK

CLR

SRCK

SER IN

DRAIN0

DRAIN1

DRAIN2

DRAIN3

DRAIN4

DRAIN5

DRAIN6

DRAIN7

SER OUT

SER IN

DRAIN0

DRAIN1

DRAIN2

DRAIN3

CLR

GND

SRCK

DRAIN7

DRAIN6

DRAIN5

DRAIN4

RCK

SER OUT

D, N, OR PW PACKAGE

(TOP VIEW)

   ! "#$ !  %#&'" ($)

(#"! "  !%$""! %$ *$ $!  $+! !#$!

!(( ,-) (#" %"$!!. ($!  $"$!!'- "'#($

$!.  '' %$$!)

Summary of content (21 pages)

PAGE 1
SLIS093C − MARCH 2000 − REVISED APRIL 2005 D Low rDS(on) . . . 7 Ω Typ D Avalanche Energy . . . 30 mJ D Eight Power DMOS Transistor Outputs of D D D D D D D, N, OR PW PACKAGE (TOP VIEW) VCC SER IN DRAIN0 DRAIN1 DRAIN2 DRAIN3 CLR G 100-mA Continuous Current 250-mA Current Limit Capability ESD Protection . . . 2500 V Output Clamp Voltage . . .
PAGE 2
SLIS093C − MARCH 2000 − REVISED APRIL 2005 description (continued) Outputs are low-side, open-drain DMOS transistors with output ratings of 33 V and 100 mA continuous sink-current capability. Each output provides a 250-mA maximum current limit at TC = 25°C. The current limit decreases as the junction temperature increases for additional device protection.
PAGE 3
SLIS093C − MARCH 2000 − REVISED APRIL 2005 schematic of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS VCC DRAIN 33 V Input 25 V 20 V 12 V GND GND absolute maximum ratings over recommended operating case temperature range (unless otherwise noted)† Logic supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Logic input voltage range, VI . . . . .
PAGE 4
SLIS093C − MARCH 2000 − REVISED APRIL 2005 recommended operating conditions Logic supply voltage, VCC High-level input voltage, VIH MIN MAX UNIT 4.5 5.5 V 0.85 VCC Low-level input voltage, VIL V 0.
PAGE 5
SLIS093C − MARCH 2000 − REVISED APRIL 2005 switching characteristics, VCC = 5 V, TC = 25°C PARAMETER TEST CONDITIONS tPLH tPHL Propagation delay time, low-to-high-level output from G tr tf Rise time, drain output Propagation delay time, high-to-low-level output from G MIN TYP CL = 30 pF, ID = 75 mA, See Figures 1, 2, and 9 tpd Propagation delay time, SRCK↓ to SEROUT f(SRCK) Serial clock frequency CL = 30 pF, See Note 8 ta trr Reverse-recovery-current ris
PAGE 6
SLIS093C − MARCH 2000 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION 5V G 50% 50% 0V 5V 15 V tPLH 1 7 15 Word Generator (see Note A) 2 10 8 Output VCC CLR SRCK ID 3 −6, 11 −14 DUT 24 V 90% 10% 10% RL = 200 Ω tr Output 0.
PAGE 7
SLIS093C − MARCH 2000 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION TP K DRAIN Circuit Under Test 0.1 A 2500 µF 250 V di/dt = 10 A/µs + L = 0.85 mH IF (see Note A) IF 15 V − 0 TP A 25% of IRM t2 t1 t3 Driver IRM RG VGG (see Note B) ta 50 Ω trr TEST CIRCUIT CURRENT WAVEFORM NOTES: A. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the TP A test point. B.
PAGE 8
SLIS093C − MARCH 2000 − REVISED APRIL 2005 TYPICAL CHARACTERISTICS PEAK AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE SUPPLY CURRENT vs FREQUENCY 6 1 VCC = 5 V TC = −40C° to 125°C ICC − Supply Current − mA 5 0.1 0.01 0.1 rDS(on) − Drain-to-Source On-State Resistance − Ω 4 3 2 1 1 0 0.
PAGE 9
SLIS093C − MARCH 2000 − REVISED APRIL 2005 TYPICAL CHARACTERISTICS SWITCHING TIME vs CASE TEMPERATURE 140 ID = 75 mA See Note A tr Switching Time − ns 120 100 tf 80 tPLH 60 tPHL 40 20 0 −50 −25 0 25 50 75 100 125 TC − Case Temperature − °C Figure 9 NOTE A: Technique should limit TJ − TC to 10°C maximum.
PAGE 10
SLIS093C − MARCH 2000 − REVISED APRIL 2005 10 MAXIMUM CONTINUOUS DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY MAXIMUM PEAK DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY 0.25 VCC = 5 V 0.20 0.15 TC = 25°C 0.10 TC = 100°C TC = 125°C 0.05 0.00 1 2 3 4 5 6 7 8 ID − Maximum Peak Drain Current of Each Output − A ID − Maximum Continuous Drain Current of Each Output − A THERMAL INFORMATION 0.
PAGE 11
SLIS093C − MARCH 2000 − REVISED APRIL 2005 THERMAL INFORMATION D PACKAGE† NORMALIZED JUNCTION - TO -AMBIENT THERMAL RESISTANCE vs PULSE DURATION RθJA − Normalized Junction-to-Ambient Thermal Resistance − °C/W 10 DC Conditions 1 d = 0.5 d = 0.2 d = 0.1 0.1 d = 0.05 d = 0.02 d = 0.01 0.01 Single Pulse 0.001 tc tw ID 0 0.0001 0.0001 0.001 0.01 0.
PAGE 12
PACKAGE OPTION ADDENDUM www.ti.
PAGE 13
PACKAGE OPTION ADDENDUM www.ti.com (3) 11-Apr-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 12-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPIC6C596DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TPIC6C596DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TPIC6C596DRG4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 12-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPIC6C596DR SOIC D 16 2500 367.0 367.0 38.0 TPIC6C596DR SOIC D 16 2500 367.0 367.0 38.0 TPIC6C596DRG4 SOIC D 16 2500 367.0 367.0 38.0 TPIC6C596DRQ1 SOIC D 16 2500 367.0 367.0 38.0 TPIC6C596PWR TSSOP PW 16 2000 367.0 367.0 35.0 TPIC6C596PWRG4 TSSOP PW 16 2000 367.0 367.0 35.
PAGE 16
PAGE 17
PAGE 18
PAGE 19
PAGE 20
PAGE 21
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.