Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsFETsTPS1101D, MOSFET

TPS1101, TPS1101Y

SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS

SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Low r

DS(on)

. . . 0.09 Ω Typ at V

= –10 V

3 V Compatible

Requires No External V

TTL and CMOS Compatible Inputs

GS(th)

= –1.5 V Max

Available in Ultrathin TSSOP Package (PW)

ESD Protection Up to 2 kV per

MIL-STD-883C, Method 3015

description

The TPS1101 is a single, low-r

DS(on)

, P-channel,

enhancement-mode MOSFET. The device has

been optimized for 3-V or 5-V power distribution

in battery-powered systems by means of the

Texas Instruments LinBiCMOS process. With a

maximum V

GS(th)

of –1.5 V and an I

DSS

of only

0.5 µA, the TPS1101 is the ideal high-side switch

for low-voltage, portable battery-management

systems where maximizing battery life is a primary

concern. The low r

DS(on)

and excellent ac

characteristics (rise time 5.5 ns typical) of the

TPS1101 make it the logical choice for

low-voltage switching applications such as power

switches for pulse-width-modulated (PWM)

controllers or motor/bridge drivers.

The ultrathin thin shrink small-outline package or

TSSOP (PW) version fits in height-restricted

places where other P-channel MOSFETs cannot.

The size advantage is especially important where

board height restrictions do not allow for an

small-outline integrated circuit (SOIC) package.

Such applications include notebook computers,

personal digital assistants (PDAs), cellular

telephones, and PCMCIA cards. For existing designs, the D-packaged version has a pinout common with other

P-channel MOSFETs in SOIC packages.

AVAILABLE OPTIONS

PACKAGED DEVICES

†

CHIP FORM

SMALL OUTLINE

(D)

TSSOP

(PW)

CHIP

FORM

(Y)

–40°C to 150°C TPS1101D TPS1101PWLE TPS1101Y

†

The D package is available taped and reeled. Add an R suffix to device type (e.g.,

TPS1101DR). The PW package is only available left-end taped and reeled (indicated by

the LE suffix on the device type; e.g., TPS1101PWLE). The chip form is tested at 25°C.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

LinBiCMOS is a trademark of Texas Instruments Incorporated.

SOURCE

GATE

DRAIN

D PACKAGE

(TOP VIEW)

SOURCE

GATE

DRAIN

PW PACKAGE

(TOP VIEW)

NC – No internal connection

D PACKAGE

PW PACKAGE

Summary of content (14 pages)

PAGE 1
TPS1101, TPS1101Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995 D D D D D D D Low rDS(on) . . . 0.09 Ω Typ at VGS = – 10 V 3 V Compatible Requires No External VCC TTL and CMOS Compatible Inputs VGS(th) = – 1.
PAGE 2
TPS1101, TPS1101Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995 schematic SOURCE ESDProtection Circuitry GATE DRAIN NOTE A: For all applications, all source terminals should be connected and all drain terminals should be connected. TPS1101Y chip information This chip, when properly assembled, displays characteristics similar to the TPS1101. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads.
PAGE 3
TPS1101, TPS1101Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† UNIT Drain-to-source voltage, VDS – 15 Gate-to-source voltage, VGS 2 or – 15 D package TA = 25°C TA = 125°C ± 0.62 PW package TA = 25°C TA = 125°C ± 0.61 D package TA = 25°C TA = 125°C ± 0.88 PW package TA = 25°C TA = 125°C ± 0.86 D package TA = 25°C TA = 125°C ± 1.
PAGE 4
TPS1101, TPS1101Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995 electrical characteristics at TJ = 25°C (unless otherwise noted) static PARAMETER VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = – 250 µA VSD Source-to-drain voltage (diode-forward voltage)† IS = – 1 A, VGS = 0 V IGSS Reverse gate current, drain short circuited to source VDS = 0 V, VGS = – 12 V IDSS Zero-gate-voltage g g drain current VDS = – 12 V V, VGS = 0 V drain-to-source
PAGE 5
TPS1101, TPS1101Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995 PARAMETER MEASUREMENT INFORMATION VGS 90% RL VDS VGS – + VDD RG 0V 10% DUT – 10 V VDS td(on) td(off) tr Figure 1. Switching-Time Test Circuit tf Figure 2.
PAGE 6
TPS1101, TPS1101Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995 TYPICAL CHARACTERISTICS DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE DRAIN CURRENT vs GATE-TO-SOURCE VOLTAGE – 10 – 10 VGS = – 8 V –9 VDS = – 10 V VGS = – 5 V TJ = 25°C –8 VGS = – 4 V I D – Drain Current – A I D – Drain Current – A –8 –7 VGS = – 3 V –6 –5 ÁÁ ÁÁ –3 VGS = – 2 V TJ = 150°C –6 ÁÁ ÁÁ –4 –2 TJ = – 40°C –4 –2 –1 TJ = 25°C 0 0 0 – 1 – 2 – 3 – 4 – 5 – 6 – 7 – 8 – 9 – 10 0
PAGE 7
TPS1101, TPS1101Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995 TYPICAL CHARACTERISTICS STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE (NORMALIZED) vs JUNCTION TEMPERATURE SOURCE-TO-DRAIN DIODE CURRENT vs SOURCE-TO-DRAIN VOLTAGE – 10 1.5 Pulse Test I SD – Source-to-Drain Diode Current – A On-State Resistance (normalized) r DS(on) – Static Drain-to-Source 1.4 VGS = – 10 V ID = – 1A 1.3 1.2 1.1 1 0.9 0.8 0.7 0.
PAGE 8
TPS1101, TPS1101Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995 TYPICAL CHARACTERISTICS GATE-TO-SOURCE VOLTAGE vs GATE CHARGE VGS – Gate-to-Source Voltage – V – 10 VDS = – 10 V ID = – 1 A TJ = 25°C –8 –6 –4 –2 0 0 2 4 6 8 10 Qg – Gate Charge – nC Figure 11 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 12
PAGE 9
TPS1101, TPS1101Y SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS079C – DECEMBER 1993 – REVISED AUGUST 1995 THERMAL INFORMATION TRANSIENT JUNCTION-TO-AMBIENT THERMAL IMPEDANCE vs PULSE DURATION DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE – 100 100 Single Pulse See Note A I D – Drain Current – A – 10 ZθJA – Transient Junction-to-Ambient Thermal Impedance – °C/W Single Pulse See Note A 0.001 s 0.01 s –1 0.1 s 1s 10 s – 0.1 DC TJ = 150°C TA = 25°C – 0.01 – 0.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.
PAGE 11
PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS1101DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS1101PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS1101DR SOIC D 8 2500 340.5 338.1 20.6 TPS1101PWR TSSOP PW 16 2000 367.0 367.0 35.
PAGE 14
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