Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsFETsTPS1120D, MOSFET

TPS1120, TPS1120Y

DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS

SLVS080A – MARCH 1994 – REVISED AUGUST 1995

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Low r

DS(on)

. . . 0.18 Ω at V

= –10 V

3-V Compatible

Requires No External V

TTL and CMOS Compatible Inputs

GS(th)

= –1.5 V Max

ESD Protection Up to 2 kV per

MIL-STD-883C, Method 3015

description

The TPS1120 incorporates two independent

p-channel enhancement-mode MOSFETs that

have been optimized, by means of the Texas

Instruments LinBiCMOS process, for 3-V or 5-V

power distribution in battery-powered systems. With a maximum V

GS(th)

of –1.5 V and an I

DSS

of only 0.5 µA,

the TPS1120 is the ideal high-side switch for low-voltage portable battery-management systems, where

maximizing battery life is a primary concern. Because portable equipment is potentially subject to electrostatic

discharge (ESD), the MOSFETs have built-in circuitry for 2-kV ESD protection. End equipment for the TPS1120

includes notebook computers, personal digital assistants (PDAs), cellular telephones, bar-code scanners, and

PCMCIA cards. For existing designs, the TPS1120D has a pinout common with other p-channel MOSFETs in

small-outline integrated circuit SOIC packages.

The TPS1120 is characterized for an operating junction temperature range, T

, from –40°C to 150°C.

AVAILABLE OPTIONS

PACKAGED DEVICES

†

CHIP FORM

SMALL OUTLINE

(D)

CHIP

FORM

(Y)

–40°C to 150°C TPS1120D TPS1120Y

†

The D package is available taped and reeled. Add an R suffix to device

type (e.g., TPS1120DR). The chip form is tested at 25°C.

Caution. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic

fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to

MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than

maximum-rated voltages to these high-impedance circuits.

LinBiCMS is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1SOURCE

1GATE

2SOURCE

2GATE

1DRAIN

2DRAIN

D PACKAGE

(TOP VIEW)

Summary of content (15 pages)

PAGE 1
TPS1120, TPS1120Y DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS080A – MARCH 1994 – REVISED AUGUST 1995 D D D D D D Low rDS(on) . . . 0.18 Ω at VGS = – 10 V 3-V Compatible Requires No External VCC TTL and CMOS Compatible Inputs VGS(th) = – 1.
PAGE 2
TPS1120, TPS1120Y DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS080A – MARCH 1994 – REVISED AUGUST 1995 schematic 1SOURCE 2SOURCE ESDProtection Circuitry ESDProtection Circuitry 1GATE 2GATE 1DRAIN† 2DRAIN† † For all applications, both drain pins for each device should be connected. TPS1120Y chip information This chip, when properly assembled, displays characteristics similar to the TPS1120C. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads.
PAGE 3
TPS1120, TPS1120Y DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS080A – MARCH 1994 – REVISED AUGUST 1995 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† UNIT Drain-to-source voltage, VDS –15 Gate-to-source voltage, VGS 2 or –15 VGS = – 2 2.7 7V VGS = – 3 V TA = 25°C TA = 125°C 5V VGS = – 4 4.5 TA = 25°C TA = 125°C ± 0.74 VGS = – 10 V TA = 25°C TA = 125°C ± 1.
PAGE 4
TPS1120, TPS1120Y DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS080A – MARCH 1994 – REVISED AUGUST 1995 electrical characteristics at TJ = 25°C (unless otherwise noted) static PARAMETER TEST CONDITIONS VGS(th) VSD Gate-to-source threshold voltage Source-to-drain voltage (diode forward voltage)† VDS = VGS, IS = – 1 A, ID = – 250 µA VGS = 0 V IGSS Reverse gate current, drain short circuited to source VDS = 0 V, IDSS Zero gate voltage drain current Zero-gate-voltage VDS = – 12 V,, VGS = 0 V VGS = –
PAGE 5
TPS1120, TPS1120Y DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS080A – MARCH 1994 – REVISED AUGUST 1995 PARAMETER MEASUREMENT INFORMATION VGS RL VDS VGS VDD RG 0V 90% – + 10% DUT – 10 V VDS td(on) td(off) tr Figure 1. Switching-Time Test Circuit POST OFFICE BOX 655303 tf Figure 2.
PAGE 6
TPS1120, TPS1120Y DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS080A – MARCH 1994 – REVISED AUGUST 1995 TYPICAL CHARACTERISTICS† Table of Graphs FIGURE Drain current vs Drain-to-source voltage 3 Drain current vs Gate-to-source voltage 4 Static drain-to-source on-state resistance vs Drain current 5 Capacitance vs Drain-to-source voltage 6 Static drain-to-source on-state resistance (normalized) vs Junction temperature 7 Source-to-drain diode current vs Source-to-drain voltage 8 Static drain-t
PAGE 7
TPS1120, TPS1120Y DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS080A – MARCH 1994 – REVISED AUGUST 1995 TYPICAL CHARACTERISTICS STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT CAPACITANCE vs DRAIN-TO-SOURCE VOLTAGE 350 0.7 VGS = 0 f = 1 MHz TJ = 25°C Ciss† TJ = 25°C 300 VGS = – 2.7 V 0.5 C – Capacitance – pF On-State Resistance – Ω r DS(on) – Static Drain-to-Source 0.6 VGS = – 3 V 0.4 VGS = – 4.5 V 0.3 VGS = –10 V 0.2 200 Coss 150 Crss‡ 100 0.1 50 0 – 0.
PAGE 8
TPS1120, TPS1120Y DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS080A – MARCH 1994 – REVISED AUGUST 1995 TYPICAL CHARACTERISTICS STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs GATE-TO-SOURCE VOLTAGE GATE-TO-SOURCE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE VGS(th) – Gate-to-Source Threshold Voltage – V r DS(on) – Static Drain-to-Source On-State Resistance – Ω 0.7 ID = – 1 A TJ = 25°C 0.6 0.5 0.4 0.3 0.2 0.1 0 –1 –3 –5 –7 –9 – 13 – 11 – 15 – 1.5 ID = – 250 µA – 1.4 – 1.3 – 1.2 – 1.
PAGE 9
TPS1120, TPS1120Y DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS080A – MARCH 1994 – REVISED AUGUST 1995 THERMAL INFORMATION DRAIN CURRENT vs DRAIN-TO-SOURCE VOLTAGE – 10 Single Pulse See Note A 0.001 s I D – Drain Current – A 0.01 s –1 0.1 s 1s – 0.1 10 s DC TJ = 150°C TA = 25°C – 0.001 – 0.
PAGE 10
TPS1120, TPS1120Y DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS080A – MARCH 1994 – REVISED AUGUST 1995 THERMAL INFORMATION The profile of the heat sinks used for thermal measurements is shown in Figure 14. Board type is FR4 with 1-oz copper and 1-oz tin/lead (63/37) plate. Use of vias or through-holes to enhance thermal conduction was avoided. Figure 15 shows a family of RθJA curves. The RθJA was obtained for various areas of heat sinks while subject to air flow. Power remained fixed at 0.
PAGE 11
TPS1120, TPS1120Y DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS SLVS080A – MARCH 1994 – REVISED AUGUST 1995 THERMAL INFORMATION Figure 16 illustrates the thermally enhanced (SO) lead frame. Attaching the two MOSFET dies directly to the source terminals allows maximum heat transfer into a power plane. Lead 1 1SOURCE 1DRAIN Lead 8 1DRAIN Lead 7 2DRAIN Lead 6 2DRAIN Lead 5 Pad 1 MOSFET 1 Lead 2 1GATE Pad 1 Lead 3 2SOURCE MOSFET 2 Lead 4 2GATE Figure 16.
PAGE 12
PACKAGE OPTION ADDENDUM www.ti.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS1120DR Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 6.4 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS1120DR SOIC D 8 2500 346.0 346.0 29.
PAGE 15
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