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SLVS333 − AUGUST 2001

       

    

www.ti.com

FEATURES

Two 340-mΩ (Typical) High-Side MOSFETs

D 200 mA Low-Dropout Voltage Regulator In

Fixed 3.3-V or Adjustable Versions

D Independent Thermal- and Short-Circuit

Protection for LDO and Each Switch

D Overcurrent Indicators With Transient Filter

D 2.9-V to 5.5-V Operating Range

D CMOS- and TTL-Compatible Enable Inputs

D 75-µA (Typical) Supply Current

D Available in 10-Pin MSOP or 14-Pin TSSOP

(PowerPAD)

D −40°C to 85°C Ambient Temperature Range

APPLICATIONS

USB Hubs and Peripherals

− Keyboards

− Zip Drives

− Speakers and Headsets

D PDAs and Portable Electronics

D DSP Power Sequencing

DESCRIPTION

Two power-distribution switches and an adjustable

(TPS2145) or fixed (TPS2147) LDO are incorporated in

one small package, providing a power management

solution that saves up to 60% in board space over

typical implementations.

Designed to meet USB 2.0 bus-powered hub

requirements, these devices also allow core and I/O

voltage sequencing in DSP applications, or power

segmentation in portable equipment. Each current-

limited switch is a 340-mΩ N-channel MOSFET capable

of supplying 200 mA of continuous current. A logic

enable compatible with 5-V logic and 3-V logic controls

each MOSFET as well as the LDO in the TPS2145. The

internal charge pump provides the gate drive controlling

the power-switch rise times and fall times, minimizing

current surges during switching. The charge pump

requires no external components.

The LDO has a drop-out voltage of only 0.35 V and with

the independent enable on the TPS2145 LDO, the LDO

can be used as an additional switch. The LDO output

range for the TPS2145 is 1 V to 3.3 V, while the

TPS2147 is fixed at 3.3 V.

The TPS2145 and TPS2147 have active-low switch

enables and the TPS2155 and TPS2157 have

active-high switch enables.

LDO and dual switch family selection guide and schematics

LDO

LDO_OUT

LDO_ADJ

OC1

OUT1

OUT2

OC2

VIN/SW1

LDO_EN

EN1

SW2

EN2

GND

TPS2145/55

TSSOP−14

LDO

OC1

OC2

EN1

SW2

EN2

GND

TPS2147/57

MSOP−10

LDO

EN2

EN1

GND

TPS2148/58

MSOP−8

LDO

EN1

EN2

GND

TPS2149/59

MSOP−8

VIN/SW1

LDO_OUT

OUT1

OUT2

VIN/SW1

LDO_EN

LDO_OUT

OUT2

OUT1

VIN

LDO_OU

OUT1

OUT2

  ! " #$%! "  &$'(#! )!%*

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PowerPAD is a trademark of Texas Instruments.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (35 pages)

PAGE 1
SLVS333 − AUGUST 2001 FEATURES D Two 340-mΩ (Typical) High-Side MOSFETs D 200 mA Low-Dropout Voltage Regulator In D D D D D D D DESCRIPTION Two power-distribution switches and an adjustable (TPS2145) or fixed (TPS2147) LDO are incorporated in one small package, providing a power management solution that saves up to 60% in board space over typical implementations. Fixed 3.
PAGE 2
SLVS333 − AUGUST 2001 AVAILABLE OPTIONS TA −40°C to 85°C PACKAGED DEVICES PACKAGE AND PIN COUNT DESCRIPTION ACTIVE LOW (SWITCH) ACTIVE HIGH (SWITCH) Adjustable LDO with LDO enable TSSOP-14 TPS2145IPWP TPS2155IPWP 3.3-V fixed LDO MSOP-10 TPS2147IDGQ TPS2157IDGQ 3.3-V Fixed LDO with LDO enable and LDO output switch MSOP-8 TPS2148IDGN TPS2158IDGN 3.
PAGE 3
SLVS333 − AUGUST 2001 recommended operating conditions VI(VIN/SWIN1) VI(SWIN2) Input voltage VI(ENx) VI(LDO_EN) Continuous output current, IO Output current limit, IO(LMT) MIN MAX 2.9 5.5 2.9 5.5 0 5.5 0 V 5.5 LDO_OUT 200 OUT1, OUT2 150 LDO_OUT 275 550 OUT1, OUT2 200 400 −40 100 Operating virtual-junction temperature range, TJ UNIT mA mA °C electrical characteristics over recommended operating junction-temperature range, 2.
PAGE 4
SLVS333 − AUGUST 2001 electrical characteristics over recommended operating junction-temperature range, 2.9 V ≤ VI(VIN/SWIN1) ≤ 5.5 V, 2.9 V ≤ VI(SWIN2) ≤ 5.
PAGE 5
SLVS333 − AUGUST 2001 electrical characteristics over recommended operating junction-temperature range, 2.9 V ≤ VI(VIN/SWIN1) ≤ 5.5 V, 2.9 V ≤ VI(SWIN2) ≤ 5.5 V, VI(ENx) = 0 V or VI(ENx) = 5 V, VI(LDO_EN) = 5 V, TJ = −40°C to 100°C (unless otherwise noted) (continued) undervoltage lockout at SWIN2 PARAMETER TEST CONDITIONS UVLO Threshold MIN TYP MAX 2.2 Hysteresis (see Note 1) 2.85 260 Deglitch (see Note 1) UNIT V mV µs 50 NOTE 1.
PAGE 6
SLVS333 − AUGUST 2001 electrical characteristics over recommended operating junction-temperature range, 2.9 V ≤ VI(VIN/SWIN1) ≤ 5.5 V, 2.9 V ≤ VI(SWIN2) ≤ 5.5 V, VI(ENx) = 0 V or VI(ENx) = 5 V, VI(LDO_EN) = 5 V, CL(LDO_OUT) = 10 µF, TJ = −40°C to 100°C (unless otherwise noted) (continued) adjustable voltage regulator (Vx = 1 V to 3.
PAGE 7
SLVS333 − AUGUST 2001 electrical characteristics over recommended operating junction-temperature range, 2.9 V ≤ VI(VIN/SWIN1) ≤ 5.5 V, 2.9 V ≤ VI(SWIN2) ≤ 5.5 V, VI(ENx) = 0 V or VI(ENx) = 5 V, VI(LDO_EN) = 5 V, TJ = −40°C to 100°C (unless otherwise noted) enable input, ENx (active low) PARAMETER VIH VIL High-level input voltage II Input current, pullup (source) TEST CONDITIONS MIN TYP MAX 2 UNIT V Low-level input voltage VI(ENx) = 0 V 0.
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SLVS333 − AUGUST 2001 TPS2145 functional block diagram 1 V to 3.3 V / 200 mA LDO VIN/SWIN1 LDO_OUT LDO_ADJ LDO_EN CS Charge Pump OUT1 Current Limit Driver OC1 EN1 Thermal Sense CS SWIN2 OUT2 Current Limit Driver OC2 EN2 Thermal Sense GND TPS2147 functional block diagram 3.3 V / 200 mA LDO VIN/SWIN1 LDO_OUT CS Charge Pump OUT1 Current Limit Driver OC1 EN1 Thermal Sense SWIN2 CS Current Limit Driver OC2 EN2 GND 8 OUT2 Thermal Sense www.ti.
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SLVS333 − AUGUST 2001 Terminal Functions TERMINAL NO. NAME PWP-14 TPS2145 EN1 TPS2155 TPS2147 14 EN1 14 EN2 13 GND 8 DESCRIPTION TPS2157 10 I Logic level enable to transfer power to OUT1 9 I Logic level enable to transfer power to OUT2 10 13 EN2 I/O DGQ-10 9 8 6 6 Ground LDO_ADJ 7 7 I User feedback for adjustable regulator LDO_EN 10 10 I Logic level LDO enable. Active high.
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SLVS333 − AUGUST 2001 detailed description (continued) enable (ENx, ENx) The logic enable disables the power switch. Both switches have independent enables and are compatible with both TTL and CMOS logic. overcurrent (OCx) The OCx open-drain output is asserted (active low) when an overcurrent condition is encountered. The output will remain asserted until the overcurrent condition is removed. current sense A sense FET monitors the current supplied to the load.
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SLVS333 − AUGUST 2001 PARAMETER MEASUREMENT INFORMATION 50% VI(ENx) 50% tpd(off) ton toff tpd(on) 90% VO(OUTx) 90% 10% 10% tr tf 90% VO(OUTx) 90% 10% 10% TIMING Figure 2.
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SLVS333 − AUGUST 2001 TYPICAL CHARACTERISTICS SWITCH TURNOFF DELAY AND FALL TIME WITH 120-µF LOAD SWITCH TURNON DELAY AND RISE TIME WITH 120-µF LOAD VI(EN) (5 V/div) VI(EN) (5 V/div) VO(OUT) (2 V/div) VO(OUT) (2 V/div) VI = 5 V TA = 25°C CL = 120 µF RL = 25 Ω VI = 5 V TA = 25°C CL = 120 µF RL = 25 Ω 0 2 4 6 8 10 12 14 t − Time − ms 16 18 0 20 4 Figure 5 8 12 16 20 24 28 t − Time − ms 32 36 40 Figure 6 LDO TURNON DELAY AND RISE TIME WITH 4.
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SLVS333 − AUGUST 2001 TYPICAL CHARACTERISTICS LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE IO(LDO_OUT) 5.25 V VI(VIN) 4.25 V (200 mA/div) ∆VO(LDO_OUT) (100 mV/div) ∆VO(LDO_OUT) (0.05 V/div) TA = 25°C CL(LDO_OUT) = 4.7 µF ESR = 1 Ω IO(LDO_OUT) = 200 mA 0 TA = 25°C CL(LDO_OUT) = 4.
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SLVS333 − AUGUST 2001 rDS(on) − Static Drain-Source On-State Resistance − Ω STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 0.6 0.55 0.5 0.45 SW1 0.4 SW2 0.35 0.3 0.25 0.2 0.15 0.1 −40 −20 0 20 40 60 80 TJ − Junction Temperature − °C 100 rDS(on) − Static Drain-Source On-State Resistance − Ω TYPICAL CHARACTERISTICS STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs SUPPLY VOLTAGE 0.38 0.37 0.36 0.35 SW1 0.34 SW2 0.33 0.32 0.31 0.3 2.
PAGE 15
SLVS333 − AUGUST 2001 TYPICAL CHARACTERISTICS UNDERVOLTAGE LOCKOUT vs JUNCTION TEMPERATURE 2.9 UVLO − Undervoltage Lockout − V 2.8 Rising 2.7 2.6 2.5 Falling 2.4 2.3 2.2 2.1 −40 −25 −10 5 20 35 50 65 80 TJ − Junction Temperature − °C 95 110 Figure 17 APPLICATION INFORMATION external capacitor requirements on power lines Ceramic bypass capacitors (0.01-µ to 0.
PAGE 16
SLVS333 − AUGUST 2001 APPLICATION INFORMATION programming the adjustable LDO regulator The output voltage of the TPS2145 adjustable regulator is programmed using an external resistor divider as shown in Figure 18. The output voltage is calculated using: ǒ Ǔ LDO_OUT + V ref 1) R1 R2 (2) where Vref = 0.8 V typical (internal reference voltage). Resistors R1 and R2 should be chosen for approximately 4-µA (minimum) divider current.
PAGE 17
SLVS333 − AUGUST 2001 APPLICATION INFORMATION overcurrent (continued) In the third condition, the load has been gradually increased beyond the recommended operating current. The current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is exceeded. The TPS2145 and TPS2147 are capable of delivering current up to the current-limit threshold without damaging the device.
PAGE 18
SLVS333 − AUGUST 2001 APPLICATION INFORMATION thermal protection Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for extended periods of time. The faults force the TPS2145 and TPS2147 into constant-current mode at first, which causes the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal to the input voltage.
PAGE 19
SLVS333 − AUGUST 2001 APPLICATION INFORMATION USB power-distribution requirements USB can be implemented in several ways, and, regardless of the type of USB device being developed, several power-distribution features must be implemented.
PAGE 20
SLVS333 − AUGUST 2001 APPLICATION INFORMATION 1.5 kΩ D+ USB Function Controller D− TPS2147 GND VIN/SW1 5V 4.7 µF 0.1 µF 3.3 V LDO LDO_OUT 10 µF 0.1 µF OC1 OUT1 EN1 External 5-V Supply SW2 4.7 µF 0.1 µF OUT2 5-V Circuitry EN2 OC2 Figure 19. TPS2147 USB Bus-Powered/Self-Powered Peripheral Application DSP applications Figure 20 shows the TPS2145 in a DSP application. DSPs use a 1.8-V core voltage and a 3.3-V I/O voltage.
PAGE 21
SLVS333 − AUGUST 2001 APPLICATION INFORMATION 4.7 µF 0.1 µF DSP TPS2145 VIN/SW1 3.3 V External Supply ADJ LDO 1.8 V 10 µF 5V 0.1 µF LDO_EN OC1 Additional 3.3-V Circuitry OUT1 EN1 SW2 4.7 µF 5-V Circuitry OUT2 0.1 µF EN2 OC2 Figure 20. TPS2145 DSP Application TPS2145 External 3.3-V Supply VIN/SW1 4.7 µF 0.1 µF ADJ LDO 1.8 V 10 µF 0.1 µF DSP LDO_EN OC1 OUT1 SVS EN1 SW2 OUT2 EN2 Additional 3.3-V Circuitry OC2 Figure 21.
PAGE 22
SLVS333 − AUGUST 2001 APPLICATION INFORMATION TPS2145 External 3.3-V Supply VIN/SW1 4.7 µF 0.1 µF 1.8 V ADJ LDO 10 µF 0.1 µF DSP LDO_EN SVS EN1 OUT1 OC1 SW2 Additional 3.3-V Circuitry OUT2 EN2 OC2 Figure 22. TPS2145 DSP With SVS Application TPS2145 External 3.3-V Supply VIN/SW1 4.7 µF 0.1 µF ADJ LDO 1.8 V 10 µF 0.1 µF DSP LDO_EN OC1 OUT1 Dual SVS EN1 SW2 OUT2 EN2 Additional 3.3-V Circuitry OC2 Figure 23.
PAGE 23
SLVS333 − AUGUST 2001 APPLICATION INFORMATION power supply sequencing DSPs typically do not require specific power sequencing between the core supply and the I/O supply. However, systems should be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper operating voltage.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (3) 11-Apr-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPS2145IPWPR HTSSOP PWP 14 2000 330.0 12.4 TPS2147IDGQR MSOPPower PAD DGQ 10 2500 330.0 12.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.9 5.6 1.6 8.0 12.0 Q1 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2145IPWPR HTSSOP PWP 14 2000 367.0 367.0 35.0 TPS2147IDGQR MSOP-PowerPAD DGQ 10 2500 358.0 335.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.