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SLVS373 − AUGUST 2001

    

    

www.ti.com

FEATURES

Complete Power Management Solution for

USB Bus-Powered Peripherals

D 3.3-V 200 mA Low-Dropout Voltage Regulator

With Enable

D 3.3-V 340-mΩ (Typ) High-Side MOSFET

D 5-V 340-mΩ (Typ) High-Side MOSFET

D Independent Thermal- and Short-Circuit

Protection for LDO and Each Switch

D 2.9-V to 5.5-V Operating Range

D CMOS- and TTL-Compatible Enable Inputs

D 75-µA (Typ) Supply Current

D Available in 8-Pin MSOP (PowerPAD)

D −40°C to 85°C Ambient Temperature Range

APPLICATIONS

USB Peripherals

− Digital Cameras

− Zip Drives

− Speakers and Headsets

DESCRIPTION

The TPS2148 incorporates two power distribution

switches and an LDO in one small package, providing

a USB peripheral power management solution that

saves up to 60% in board space over typical

implementations.

The TPS2148 meets USB 2.0 bus-powered peripheral

requirements. An integrated LDO regulates the 5-V bus

power down to 3.3 V for the USB controller, and a

MOSFET switch that is internally connected to the

output of the LDO simplifies meeting the suspend and

enumeration current requirements imposed by the USB

specification.

A second switch is available to support a downstream

port, stage power to a second voltage regulator, or

disable power to selected circuitry in power-save

modes.

Each power-distribution switch is capable of supplying

200 mA of continuous current, and the independent

logic enables are compatible with 5-V logic and 3-V

logic. The switches and the LDO are designed with

controlled rise times and fall times to minimize current

surges.

The TPS2148 has active-low enables while the

TPS2158 has active-high enables.

LDO and dual switch family selection guide and schematics

LDO

LDO_OUT

LDO_ADJ

OC1

OUT1

OUT2

OC2

VIN/SW1

LDO_EN

EN1

SW2

EN2

GND

TPS2145/55

TSSOP−14

LDO

OC1

OC2

EN1

SW2

EN2

GND

TPS2147/57

MSOP−10

LDO

EN2

EN1

GND

TPS2148/58

MSOP−8

LDO

EN1

EN2

GND

TPS2149/59

MSOP−8

VIN/SW1

LDO_OUT

OUT1

OUT2

VIN/SW1

LDO_EN

LDO_OUT

OUT2

OUT1

VIN

LDO_OU

OUT1

OUT2

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PowerPAD is a trademark of Texas Instruments.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (22 pages)

PAGE 1
SLVS373 − AUGUST 2001 FEATURES D Complete Power Management Solution for D D D D D D D D D DESCRIPTION USB Bus-Powered Peripherals 3.3-V 200 mA Low-Dropout Voltage Regulator With Enable 3.3-V 340-mΩ (Typ) High-Side MOSFET 5-V 340-mΩ (Typ) High-Side MOSFET Independent Thermal- and Short-Circuit Protection for LDO and Each Switch 2.9-V to 5.
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SLVS373 − AUGUST 2001 AVAILABLE OPTIONS TA PACKAGE AND PIN COUNT DESCRIPTION −40°C to 85°C PACKAGED DEVICES ACTIVE LOW (SWITCH) ACTIVE HIGH (SWITCH) Adjustable LDO with LDO enable TSSOP-14 TPS2145IPWP TPS2155IPWP 3.3-V fixed LDO MSOP-10 TPS2147IDGQ TPS2157IDGQ 3.3-V Fixed LDO with LDO enable and LDO output switch MSOP-8 TPS2148IDGN TPS2158IDGN 3.3-V Fixed LDO, shared input with switches MSOP-8 TPS2149IDGN TPS2159IDGN NOTE: All options available taped and reeled.
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SLVS373 − AUGUST 2001 recommended operating conditions VI(VIN/SWIN1) VI(ENx) Input voltage VI(LDO_EN) LDO_OUT Continuous output current, IO Output current limit, IO(LMT) MIN MAX 2.9 5.5 0 5.5 0 5.5 UNIT V 200 OUT1, OUT2 150 mA LDO_OUT 275 550 OUT1, OUT2 200 400 −40 100 °C MAX UNIT Operating virtual-junction temperature range, TJ mA electrical characteristics over recommended operating junction-temperature range, 2.9 V ≤ VI(VIN/SWIN1) ≤ 5.
PAGE 4
SLVS373 − AUGUST 2001 electrical characteristics over recommended operating junction-temperature range, 2.9 V ≤ VI(VIN/SWIN1) ≤ 5.
PAGE 5
SLVS373 − AUGUST 2001 electrical characteristics over recommended operating junction-temperature range, 2.9 V ≤ VI(VIN/SWIN1) ≤ 5.5 V, VI(ENx) = 0 V, VI(LDO_EN) = 5 V, CL(LDO_OUT) = 10 µF, TJ = −40°C to 100°C (unless otherwise noted) 3.3 V LDO PARAMETER TEST CONDITIONS† MIN TYP MAX UNIT 3.20 3.3 3.40 V Output voltage, dc VI(VIN/SWIN1) = 4.25 V to 5.25 V, IO(LDO_OUT) = 0.5 mA to 200 mA Dropout voltage VI(VIN/SWIN1) = 3.2 V, IO = 200 mA, IO(OUT) = 150 mA 0.
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SLVS373 − AUGUST 2001 electrical characteristics over recommended operating junction-temperature range, 2.9 V ≤ VI(VIN/SWIN1) ≤ 5.5 V, 2.9 V ≤ VI(SWIN2) ≤ 5.5 V, VI(ENx) = 0 V, VI(LDO_EN) = 5 V, TJ = −40°C to 100°C (unless otherwise noted) enable input, ENx (active low) PARAMETER VIH VIL High-level input voltage II Input current, pullup (source) TEST CONDITIONS MIN TYP MAX 2 UNIT V Low-level input voltage VI(ENx) = 0 V 0.
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SLVS373 − AUGUST 2001 TPS2148 functional block diagram 3.3 V / 200 mA LDO VIN/SWIN1 LDO_OUT LDO_EN CS Charge Pump Driver OUT2 Current Limit EN2 Thermal Sense OUT1 CS Driver Current Limit EN2 Thermal Sense GND Terminal Functions TERMINAL NAME NO. TPS2148 EN1 EN1 I/O DESCRIPTION TPS2158 8 I Logic level enable to transfer power to OUT1 7 I Logic level enable to transfer power to OUT2 8 EN2 EN2 7 GND 5 5 LDO_EN 6 6 I Logic level LDO enable. Active high.
PAGE 8
SLVS373 − AUGUST 2001 detailed description VIN/SWIN1 The VIN/SWIN1 serves as the input to the internal LDO and as the input to one N-channel MOSFET. The 3.3-V LDO has a dropout voltage of 0.35 V and is rated for 200 mA of continuous current. The power switch is an N-channel MOSFET with a maximum on-state resistance of 580 mΩ. Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when disabled.
PAGE 9
SLVS373 − AUGUST 2001 TYPICAL CHARACTERISTICS SWITCH TURNON DELAY AND RISE TIME WITH 1-µF LOAD SWITCH TURNOFF DELAY AND FALL TIME WITH 1-µF LOAD VI(EN) (5 V/div) VI(EN) (5 V/div) VO(OUT) (2 V/div) VO(OUT) (2 V/div) VI = 5 V TA = 25°C CL = 1 µF RL = 25 Ω VI = 5 V TA = 25°C CL = 1 µF RL = 25 Ω 0 0.4 0.8 1.2 1.6 2 2.4 2.8 t − Time − ms 3.2 3.6 0 4.2 0.4 0.8 1.2 Figure 2 1.6 2 2.4 2.8 t − Time − ms 3.2 3.6 4.
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SLVS373 − AUGUST 2001 TYPICAL CHARACTERISTICS SHORT-CIRCUIT CURRENT, SWITCH ENABLED INTO A SHORT LDO TURNON DELAY AND RISE TIME WITH 4.7-µF LOAD VI(EN) (5 V/div) VI = 5 V TA = 25°C CL = 4.7 µF RL = 13.2 Ω VI(LDO_EN) (5 V/div) VO(LDO_OUT) (1 V/div IO(OUT) (100 mA/div) 0 1 2 3 4 5 6 t − Time − ms 7 8 9 10 0 Figure 6 0.8 1.2 1.6 2 2.4 2.8 t − Time − ms 3.2 3.6 4.2 Figure 7 LOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE IO(LDO_OUT) 5.25 V VI(VIN) 4.
PAGE 11
SLVS373 − AUGUST 2001 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE 140 140 120 120 I DD − Supply Current − µ A I DD − Supply Current − µ A SUPPLY CURRENT vs JUNCTION TEMPERATURE 100 80 60 40 80 60 40 20 20 0 −40 100 −20 0 20 40 60 80 0 2.5 100 3 TJ − Temperature − °C rDS(on) − Static Drain-Source On-State Resistance − Ω STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE 0.6 0.55 0.5 0.45 SW1 0.4 SW2 0.35 0.3 0.25 0.2 0.15 0.1 −40 −20 5 5.
PAGE 12
SLVS373 − AUGUST 2001 TYPICAL CHARACTERISTICS SHORT CIRCUIT CURRENT vs SUPPLY VOLTAGE 400 400 380 380 360 360 Short Circuit Current − mA Short Circuit Current − mA SHORT CIRCUIT CURRENT vs JUNCTION TEMPERATURE 340 320 300 SW1 280 SW2 260 340 320 SW1 300 280 260 240 240 220 220 200 −40 −20 0 20 40 60 80 TJ − Free-Air Temperature − °C 200 2.5 100 SW2 3 3.5 4 4.5 VCC − Supply Voltage Figure 14 Figure 15 UNDERVOLTAGE LOCKOUT vs JUNCTION TEMPERATURE 2.
PAGE 13
SLVS373 − AUGUST 2001 APPLICATION INFORMATION Upstream Data Port 1.5 kΩ D+ D− GND USB Function Controller TPS2148 5V 4.7 µF 0.1 µF 5-V Circuitry 3.3 V LDO 10 µF 0.1 µF 3.3 V Circuitry Figure 17. Example of a Peripheral Design With TPS2148 external capacitor requirements on power lines A ceramic bypass capacitor (0.01-µF to 0.1-µF) between VIN/SWIN1 and GND, close to the device, is recommended to improve load transient response and noise rejection. A bulk capacitor (4.
PAGE 14
SLVS373 − AUGUST 2001 APPLICATION INFORMATION power dissipation and junction temperature The main source of power dissipation for the TPS2148 and TPS2158 comes from the internal voltage regulator and the N-channel MOSFETs. Checking the power dissipation and junction temperature is always a good design practice and it starts with determining the rDS(on) of the N-channel MOSFET according to the input voltage and operating temperature.
PAGE 15
SLVS373 − AUGUST 2001 APPLICATION INFORMATION thermal protection Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for extended periods of time. The faults force the TPS2148 and TPS2158 into constant-current mode at first, which causes the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across the switch is equal to the input voltage.
PAGE 16
SLVS373 − AUGUST 2001 APPLICATION INFORMATION USB power distribution requirements USB can be implemented in several ways, and, regardless of the type of USB device being developed, several power-distribution features must be implemented.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.