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 

 

SLVS399A − JANUARY 2002 − REVISED MAY 2006

        

    

www.ti.com

FEATURES

Complete Power Management Solution for

USB High-Power Peripherals

D 250 mA Low-Dropout Regulator (LDO) With

Enable and 325 mA (Typ) Current Limit

D LDO Supports 2.7 V to 5.5 V V

and 0.9 V to

3.3 V Adjustable V

OUT

D 40 mΩ (Typ) High-Side MOSFET With Dual

Current Limit

D Undervoltage Lockout and Power Good for

LDO and Switch

D CMOS- and TTL-Compatible Enable Inputs

D 85 µA (Typ) Supply Current

D 5 µA (Typ) Standby Supply Current

D Available in 14-Pin HTSSOP (PowerPAD)

D −40°C to +85°C Ambient Temperature Range

D Alternative to TPS2148/58 3.3-V LDO With

3.3-V Switch and 5-V Switch

APPLICATIONS

High-Power USB Peripherals

− ADSL Modems

− Digital Still and PC Cameras

− Zip Drives

− Speakers

D DSP Sequencing

DESCRIPTION

The TPS2140/41/50/51 is a USB 1.0 and 2.0

Specification-compatible IC containing a dual-current-

limiting power switch and an adjustable low dropout

regulator (LDO). Both the switch and LDO limit inrush

current by controlling the turnon slew rate. The unique

dual-current-limiting feature of the switch allows USB

peripherals to utilize high-value capacitance at the

output of the switch, while keeping the inrush current

low. During turnon, the switch limits the current

delivered to the capacitive load to less than 100 mA.

When the output voltage from the switch reaches about

93% of the input voltage, the switch power good output

goes high, and the switch current limit increases to

800mA (minimum), at which point higher current loads

can be turned on. The higher current limit provides short

circuit protection while allowing the peripheral to draw

maximum current from the USB bus.

The switch and LDO function independently, providing

flexibility in DSP applications requiring separate core

and I/O voltages. For example, in a DSP application

operating from a 3.3-V rail, the LDO can supply the DSP

core voltage down to 0.9 V, while the switch powers the

3.3-V (typical) DSP I/O supply. If supply sequencing is

required, the LDO power good output can be used to

enable the switch.

AVAILABLE OPTIONS

TARGET

PACKAGE

PACKAGED DEVICES

DESCRIPTION

TARGET

APPLICATION

PACKAGE

AND PIN

COUNT

ACTIVE LOW

(SWITCH)

ACTIVE HIGH

(SWITCH)

−40°C to 85°C

Adjustable LDO and 3.3 V switch with dual current

limit

DSP HTSSOP-14 TPS2140IPWP TPS2150IPWP

−40°C to 85°C

Adjustable LDO and 5 V switch with dual current

limit

USB HTSSOP-14 TPS2141IPWP TPS2151IPWP

NOTE: All options available taped and reeled. Add an R suffix (e.g., TPS2140IPWPR)

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments. USB is a trademark of Universal Serial Bus Association.

All other trademarks are the property of their respective owners.

Summary of content (32 pages)

PAGE 1
SLVS399A − JANUARY 2002 − REVISED MAY 2006 FEATURES D Complete Power Management Solution for D D D D D D D D D D DESCRIPTION The TPS2140/41/50/51 is a USB 1.0 and 2.0 Specification-compatible IC containing a dual-currentlimiting power switch and an adjustable low dropout regulator (LDO). Both the switch and LDO limit inrush current by controlling the turnon slew rate.
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SLVS399A − JANUARY 2002 − REVISED MAY 2006 TPS2140/41/50/51 PWP PACKAGE (TOP VIEW) SW_PG SW_IN SW_IN LDO_IN SW_EN† LDO_EN GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 SW_PLDN SW_OUT SW_OUT LDO_OUT LDO_PLDN ADJ LDO_PG † Pin 5 is active high for TPS2150 and TPS2151. USB peripheral application D+ D− TPS2151 GND LDO_PLDN 5V 1.5 kΩ USB Function Controller LDO_OUT LDO_IN LDO ADJ LDO_EN LDO_PG SW_IN SW_OUT Switch SW_PLDN SW_PG SW_EN 2 www.ti.
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SLVS399A − JANUARY 2002 − REVISED MAY 2006 functional block diagram CS SW_IN SW_OUT SW_OUT 2-Level Current Limit SW_PG Driver VREF SW_PLDN SW_EN† VCC Select Charge Pump Thermal Sense VREF 0.9 V to 3.3 V 250 mA LDO LDO_IN LDO_PG ADJ LDO_OUT LDO_PLDN LDO_EN GND † The pin is active low for TPS2140 and TPS2141, with an internal pullup. The pin is active high for TPS2150 and TPS2151, with an internal pulldown. Terminal Functions TERMINAL NAME NO.
PAGE 4
SLVS399A − JANUARY 2002 − REVISED MAY 2006 detailed description GND Ground SW_IN SW_IN is the input to an integrated N-channel MOSFET, which has a maximum on-state resistance of 65 mΩ. Configured as a high-side switch, the power switch prevents current, flow from OUT to IN and IN to OUT when disabled. The power switch is rated at 500 mA, continuous current and has a dual current limit feature.
PAGE 5
SLVS399A − JANUARY 2002 − REVISED MAY 2006 detailed description (continued) LDO_OUT LDO_OUT is the output of the internal LDO. It has an output voltage range of 0.9 V to 3.3 V. LDO_EN LDO_EN is used to enable or disable the internal LDO and is compatible with CMOS and TTL logic. LDO_EN is an active high input. ADJ ADJ is used to adjust the LDO output voltage (LDO_OUT) anywhere between 0.9 V and 3.
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SLVS399A − JANUARY 2002 − REVISED MAY 2006 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Input voltage range for bus switch and LDO: VI(SW_IN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V VI(LDO_IN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V Output voltage range for bus switch and LDO:VO(SW_OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . .
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SLVS399A − JANUARY 2002 − REVISED MAY 2006 electrical characteristics over recommended operating junction temperature range, VI(SW_IN) = 3.3 V for TPS2140/50, VI(SW_IN) = 5 V for TPS2141/51, VI(LDO_IN) = 5 V, all outputs unloaded (unless otherwise noted) general PARAMETER TEST CONDITIONS MIN TYP MAX TPS2140, TPS2150 2.7 V < VI(SW_IN) < 5.5 V, VI(LDO_IN) = 0, VI(SW_EN) = 5.5 V or VI(/SW_EN) = 0 V, VI(LDO_EN) = 0 V, No load 85 110 TPS2141, TPS2151 4.
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SLVS399A − JANUARY 2002 − REVISED MAY 2006 electrical characteristics over recommended operating junction temperature range, VI(SW_IN) = 3.3 V for TPS2140/50, VI(SW_IN) = 5 V for TPS2141/51, VI(LDO_IN) = 5 V, all outputs unloaded (unless otherwise noted) (continued) power switch TEST CONDITIONS† PARAMETER TPS2140, TPS2150 Switch on resistance (SW_IN to SW_OUT) TPS2141, TPS2151 Switch current limit MIN TJ = 25°C, I = 500 mA, VI(SW_EN) = 3.
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SLVS399A − JANUARY 2002 − REVISED MAY 2006 electrical characteristics over recommended operating junction temperature range, VI(SW_IN) = 3.3 V for TPS2140/50, VI(SW_IN) = 5 V for TPS2141/51, VI(LDO_IN) = 5 V, all outputs unloaded (unless otherwise noted) (continued) adjustable voltage regulator (Vset = 0.9 V to 3.3 V) PARAMETER TEST CONDITIONS MIN TYP MAX VO(LDO_OUT) Output voltage total tolerance VI(LDO_IN) = Vset + 0.6 V to 5.5 V and VI(LDO_IN)> 2.
PAGE 10
SLVS399A − JANUARY 2002 − REVISED MAY 2006 electrical characteristics over recommended operating junction temperature range, VI(SW_IN) = 3.
PAGE 11
SLVS399A − JANUARY 2002 − REVISED MAY 2006 PARAMETER MEASUREMENT INFORMATION VO(SW_OUT) VO(LDO_OUT) IO CL IO CL LOAD CIRCUIT LOAD CIRCUIT VOLTAGE WAVEFORMS SW_EN 50% VDD 50% LDO_EN 50% VDD 50% GND GND tpd(off) tpd(on) VO(SW_OUT) tpd(off) VI(SW_IN) 90% 10% GND tpd(on) VO(LDO_OUT) Propagation Delay (SW_OUT) tr tr VI(SW_IN) 90% 10% VO(LDO_OUT) 50% LDO_EN GND 50% VO(SW_OUT) VDD GND toff VI(SW_IN) 90% 10% GND 50% toff ton V(SET) Rise/Fall
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SLVS399A − JANUARY 2002 − REVISED MAY 2006 PARAMETER MEASUREMENT INFORMATION VI (SW_EN) 5 V/div VI (SW_EN) 5 V/div LDO_EN = 5 V LDO_EN = 5 V VO (SW_OUT) 5 V/div VO (SW_OUT) 5 V/div LDO_EN = 0 V LDO_EN = 0 V VO (SW_OUT) 5 V/div VO (SW_OUT) 5 V/div t − Time − 200 µs/div t − Time − 1 ms/div Figure 3. Switch Turnon Delay and Rise Time With 10-µF Load (SW_OUT Shorted With SW_PLDN) Figure 4.
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SLVS399A − JANUARY 2002 − REVISED MAY 2006 PARAMETER MEASUREMENT INFORMATION VI (SW_EN) 5 V/div VI (SW_EN) 5 V/div CL(SW_OUT) = 600 µF CL(SW_OUT) = 10 µF CL(SW_OUT) = 120 µF II (SW_IN) 50 m A/div II (SW_IN) 0.1 A/div t − Time − 1 ms/div t − Time − 5 ms/div Figure 7. Switch Turnon Inrush Current With Different Load Capacitance Figure 8.
PAGE 14
SLVS399A − JANUARY 2002 − REVISED MAY 2006 PARAMETER MEASUREMENT INFORMATION VI (LDO_EN) 5 V/div VO(LDO_OUT) 1 V/div II (LDO_IN) 0.2 A/div II (LDO_IN) 0.2 A/div t − Time − 1 ms/div t − Time − 1 ms/div Figure 11. LDO Short-Circuit Current, With LDO Enabled Into a Short Circuit Figure 12. LDO Short-Circuit Current, With Short Circuit Connected Into Enabled LDO CL = 4.7 µF ESR = 1 Ω 5.5 V 3.3 V VO(LDO_OUT) 0.2 V/div VI (LDO_IN) 1 V/div 3.8 V 3.
PAGE 15
SLVS399A − JANUARY 2002 − REVISED MAY 2006 PARAMETER MEASUREMENT INFORMATION LDO TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE vs LOAD CURRENT LDO TYPICAL REGIONS OF STABILITY EQUIVALENT SERIES RESISTANCE vs LOAD CURRENT 100 VI = 2.7∼5 V, VO = 0.9 V, CO = 4.7 µF LDO Typical Regions of Stability Equivalent Series Resistance − Ω LDO Typical Regions of Stability Equivalent Series Resistance − Ω 100 Max ESR 10 1 VI = 2.7∼5 V, VO = 0.
PAGE 16
SLVS399A − JANUARY 2002 − REVISED MAY 2006 PARAMETER MEASUREMENT INFORMATION SWITCH STATIC DRAIN-SOURCE ON-STATE RESISTANCE vs JUNCTION TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE 140 60 I CC − Supply Current − µ A 100 rds(on) − Switch Static Drain-Source On-State Resistance − Ω SW = On, LDO = On 120 SW = Off, LDO = On 80 60 SW = On, LDO = Off 40 SW = Off, LDO = Off 20 0 2.5 3 3.5 4 4.
PAGE 17
SLVS399A − JANUARY 2002 − REVISED MAY 2006 PARAMETER MEASUREMENT INFORMATION LDO SHORT-CIRCUIT CURRENT vs JUNCTION TEMPERATURE 322 80 321 I OS − LDO Short-Circuit Current − mA 90 70 60 50 40 30 20 10 0 2.5 3 3.5 4 4.5 VCC − Supply Voltage − V 5 320 319 318 317 316 315 314 313 −50 5.
PAGE 18
SLVS399A − JANUARY 2002 − REVISED MAY 2006 APPLICATION INFORMATION external capacitor requirements on power lines Ceramic bypass capacitors (0.01 µF to 0.1 µF) between SW_IN and GND and LDO_IN and GND, close to the device, are recommended to improve load transient response and noise rejection. Bulk capacitors (4.
PAGE 19
SLVS399A − JANUARY 2002 − REVISED MAY 2006 APPLICATION INFORMATION programming the adjustable LDO regulator (continued) Table 1. Output Voltage Programming Guide OUTPUT VOLTAGE R1 R2 3.3 619 kΩ 200 kΩ Cf NR† 3.0 549 kΩ 200 kΩ NR† 2.5 422 kΩ 200 kΩ 2 pF 1.8 249 kΩ 200 kΩ 6 pF 1.5 174 kΩ 200 kΩ 10.3 pF 49.9 kΩ 200 kΩ 46 pF 1.0 † NR − Not required overcurrent When an overcurrent condition is detected, the device maintains a constant output current.
PAGE 20
SLVS399A − JANUARY 2002 − REVISED MAY 2006 APPLICATION INFORMATION power dissipation and junction temperature The major source of power dissipation for the TPS2140/41/50/51 comes from the internal voltage regulator and the N-channel MOSFET. Checking the power dissipation and junction temperature is always a good design practice and it starts with determining the rDS(on) of the N-channel MOSFET according to the input voltage and operating temperature.
PAGE 21
SLVS399A − JANUARY 2002 − REVISED MAY 2006 APPLICATION INFORMATION undervoltage lockout (UVLO) An undervoltage lockout ensures that the device (LDO and switch) is in the off state at power up. The UVLO also keeps the device from being turned on until the power supply has reached the start threshold (see undervoltage lockout table), even if the switches are enabled.
PAGE 22
SLVS399A − JANUARY 2002 − REVISED MAY 2006 APPLICATION INFORMATION USB power-distribution requirements (continued) The feature set of the TPS2140/41/50/51 allows them to meet the requirements of functions. The integrated current-limiting is required by hubs and peripheral functions. The logic-level enable and controlled rise times meet the need of both input and output ports on bus-powered hubs, as well as the input ports for bus-powered functions.
PAGE 23
SLVS399A − JANUARY 2002 − REVISED MAY 2006 APPLICATION INFORMATION DSP applications Figure 28 shows the TPS2150 in a DSP application. DSPs use 1.8-V core voltage and 3.3-V I/O voltage. In this type of application the TPS2150 adjustable LDO is configured for a 1.8-V output specifically for the DSP core voltage. The additional 3.3-V circuitry is powered through the switch of the TPS2150 only after the DSP is up and running. 3.3 V Power Supply TPS2150 LDO_PLDN 4.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 7-May-2007 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TPS2140IPWPR HTSSOP PWP 14 2000 330.0 12.4 TPS2141IPWPR HTSSOP PWP 14 2000 330.0 TPS2150IPWPR HTSSOP PWP 14 2000 330.0 TPS2151IPWPR HTSSOP PWP 14 2000 330.0 6.9 5.6 1.6 8.0 12.0 Q1 12.4 6.9 5.6 1.6 8.0 12.0 Q1 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2140IPWPR HTSSOP PWP 14 2000 367.0 367.0 35.0 TPS2141IPWPR HTSSOP PWP 14 2000 367.0 367.0 35.0 TPS2150IPWPR HTSSOP PWP 14 2000 367.0 367.0 35.0 TPS2151IPWPR HTSSOP PWP 14 2000 367.0 367.0 35.
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