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SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005

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D Fully Integrated V

and V

Switching for

Single-Slot PC Card Interface

D Low r

DS(on)

(70-mΩ 5-V V

Switch and

3.3-V V

Switch)

D Compatible With Industry-Standard

Controllers

D 3.3-V Low-Voltage Mode

D Meets PC Card Standards

D 12-V Supply Can Be Disabled Except

During 12-V Flash Programming

D Short-Circuit and Thermal Protection

D Space-Saving 16-Pin SSOP (DB) and 20-Pin

HTSSOP (PWP)

D Compatible With 3.3-V, 5-V, and 12-V PC

Cards

D Break-Before-Make Switching

description

The TPS2211A PC Card power-interface switch

provides an integrated power-management solu-

tion for a single PC Card. All of the discrete power

MOSFETs, a logic section, current limiting, and

thermal protection for PC Card control are

combined on a single integrated circuit, using the

Texas Instruments LinBiCMOS process. The

circuit allows the distribution of 3.3-V, 5-V, and/or

12-V card power, and is compatible with many PCMCIA controllers.

The current-limiting feature eliminates the need for fuses, which reduces component count and

improves reliability. Current-limit reporting can help the user isolate a system fault to the PC Card. controllers.

The current-limiting feature eliminates the need for fuses, which reduces component count and

improves reliability. Current-limit reporting can help the user isolate a system fault to the PC Card.

The TPS2211A features a 3.3-V low-voltage mode that allows for 3.3-V switching without the need for 5 V. Bias

power can be derived from either the 3.3-V or 5-V inputs. This facilitates low-power system designs such as

sleep mode and pager mode where only 3.3 V is available.

End equipment for the TPS2211A includes notebook computers, desktop computers, personal digital assistants

(PDAs), digital cameras, and bar-code scanners.

AVAILABLE OPTIONS

PACKAGED DEVICE

PLASTIC SMALL OUTLINE

(DB)

PLASTIC SMALL OUTLINE

(PW)

PowerPAD

PLASTIC SMALL OUTLINE

(PWP)

−40°C to 85°C

TPS2211AIDB

TPS2211APW TPS2211APWP

The DB, PW, and PWP packages are only available left-end taped and reeled (indicated by the R suffix on the device type,

e.g. TPS2211AIDBR).

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PC Card is a trademark of PCMCIA (Personal Computer Memory Card International Association).

LinBiCMOS, PowerPAD are trademarks of Texas Instruments.

VCCD0

VCCD1

3.3V

GND

SHDN

VPPD0

VPPD1

AVCC

AVPP

12V

DB PACKAGE

†

(TOP VIEW)

†

TPS2211A is pin-for-pin compatible with TPS2211 and

TPS2212.

VCCD0

VCCD1

3.3 V

5 V

GND

12 V

SHDN

VPPD0

VPPD1

AVCC

AVPP

PW and PWP

PACKAGE

(TOP VIEW)

‡

NC − No internal connection

‡

Must be tied together externally as close to the device as

possible.

PowerPAD applies to PWP package only.

See Note

Summary of content (28 pages)

PAGE 1
SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 D Fully Integrated VCC and Vpp Switching for DB PACKAGE† (TOP VIEW) Single-Slot PC Card Interface D Low rDS(on) (70-mΩ 5-V VCC Switch and VCCD0 VCCD1 3.3V 3.3V 5V 5V GND OC 3.3-V VCC Switch) D Compatible With Industry-Standard Controllers D 3.
PAGE 2
SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 SELECTION GUIDE VCC Vpp 3.3-V TYPICAL rDS(on) (Ω) 5-V TYPICAL rDS(on) (Ω) RECOMMENDED MAXIMUM OUTPUT CURRENT (A) TPS2211AIDB 0.07 0.07 1 4 2 0.15 TPS2211APW 0.07 0.07 1 4 2 0.15 TPS2211APWP 0.07 0.07 1 4 2 0.15 TPS2211IDB 0.048 0.05 1 4 1 0.15 TPS2212IDB 0.16 0.16 0.25 4 1 0.15 DEVICE 3.
PAGE 3
SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION PW, PWP DB 3.3V 3, 4 3, 4 I 3.3-V VCC input for card power and/or chip power if 5 V is not present 5V 5, 6 5, 6 I 5-V VCC input for card power and/or chip power 12V 10 9 I 12-V Vpp input card power AVCC 13, 14, 15, 16 11, 12, 13 O Switched output that delivers 0 V, 3.
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SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 recommended operating conditions Input voltage, VI Output current MIN MAX UNIT VI(5V) VI(3.3V) 0 5.25 V 0 5.25 V VI(12V) IO(AVCC) 0 13.5 V 1 IO(AVPP) Operating virtual junction temperature, TJ A 150 mA −40 125 °C TYP MAX UNIT 70 120 70 120 TA = 25°C TA = 25°C 4 6 4 6 TA = 25°C Ipp at 10 mA 1 2 0.3 0.8 V 0.1 0.
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SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 switching characteristics‡ TEST CONDITIONS§ PARAMETER MIN TYP Rise times, output VO(AVCC) (5 V) VO(AVPP) (12 V) 2.8 tr Fall times, output VO(AVCC) (5 V) VO(AVPP) (12 V) 5 tf tpd Propagation delay (see Figure1) MAX UNIT 6 ms 19 VI(VPPD0) to VO(AVPP) (12 V) ton toff 7 2.8 VI(VCCD1) to VO(AVCC) (3.3 V) ton toff VI(VCCD0) to VO(AVCC) (5 V) ton toff 3.
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SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 PARAMETER MEASUREMENT INFORMATION VCCD0 = 3.3 V VCCD0 = 3.3 V VCCD1 (2 V/div) VCCD1 (2 V/div) AVCC (2 V/div) AVCC (2 V/div) 0 1 2 3 4 5 6 7 8 0 9 5 10 t − Time − ms Figure 2. AVCC Propagation Delay and Rise Time With 1-µF Load, 3.3-V Switch 30 35 40 45 Figure 3. AVCC Propagation Delay and Fall Time With 1-µF Load, 3.3-V Switch VCCD0 = 3.3 V VCCD0 = 3.
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SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 PARAMETER MEASUREMENT INFORMATION VCCD0 (2 V/div) VCCD0 (2 V/div) AVCC (2 V/div) AVCC (2 V/div) VCCD1 = 5 V 0 1 2 3 4 5 t − Time − ms 6 7 8 9 Figure 6. AVCC Propagation Delay and Rise Time With 1-µF Load, 5-V Switch VCCD1 = 5 V 0 5 10 15 20 25 t − Time − ms 30 35 40 45 Figure 7.
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SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 PARAMETER MEASUREMENT INFORMATION VPPD1 = 0 V VPPD0 (2 V/div) VPPD0 (2 V/div) AVPP (5 V/div) AVPP (5 V/div) VPPD1 = 0 V 0 0.2 0.4 0.6 0.8 1 1.2 t − Time − ms 1.4 1.6 0 1.8 Figure 10. AVPP Propagation Delay and Rise Time With 1-µF Load, 12-V Switch 1 2 3 4 5 t − Time − ms 6 7 8 9 Figure 11.
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SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 TYPICAL CHARACTERISTICS Table of Graphs FIGURE ICC(5V) ICC(3.3V) Supply current vs Junction temperature 14 Supply current vs Junction temperature 15 rDS(on) Static drain-source on-state resistance, 5-V VCC switch vs Junction temperature 16 rDS(on) Static drain-source on-state resistance, 3.
PAGE 10
SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 3.
PAGE 11
SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 TYPICAL CHARACTERISTICS 3.3-V AVCC SWITCH 12-V AVCC SWITCH OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 12 3.28 −40°C VO(AVPP) − Output Voltage − V VO(AVCC) − Output Voltage − V 3.3 25°C 3.26 85°C 3.24 125°C 3.22 3.2 0 0.2 0.4 0.6 0.8 11.95 25°C 11.9 85°C 11.85 125°C 11.8 11.75 1 −40°C 0 0.03 IO(AVCC) − Output Current − A 0.
PAGE 12
SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 TYPICAL CHARACTERISTICS I OS(AVPP) − Short-Circuit Output Current − mA SHORT-CIRCUIT OUTPUT CURRENT vs JUNCTION TEMPERATURE 0.33 0.32 0.31 0.3 0.29 0.28 0.27 0.
PAGE 13
SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 APPLICATION INFORMATION designing for voltage regulation The current PCMCIA specification for output voltage regulation of the 5-V output is 5% (250 mV). In a typical PC power-system design, the power supply has an output voltage regulation (VPS(reg)) of 2% (100 mV).
PAGE 14
SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 APPLICATION INFORMATION 12-V supply not required Most PC Card switches use the externally supplied 12 V to power gate drive and other chip functions, which require that power be present at all times. The TPS2211A offers considerable power savings by using an internal charge pump to generate the required higher voltages from the 5-V input.
PAGE 15
SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 APPLICATION INFORMATION calculating junction temperature The switch resistance, rDS(on), is dependent on the junction temperature, TJ, of the die and the current through the switch. To calculate TJ, first find rDS(on) from Figures 16 through 18 using an initial temperature estimate about 50°C above ambient.
PAGE 16
SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 APPLICATION INFORMATION TPS2211A control logic AVPP CONTROL SIGNALS INTERNAL SWITCH SETTINGS SHDN VPPD0 VPPD1 S4 1 0 0 1 0 1 1 1 OUTPUT S5 S6 AVPP CLOSED OPEN OPEN 0V OPEN CLOSED OPEN AVCC† 0 OPEN OPEN CLOSED VPP (12 V) 1 1 1 OPEN OPEN OPEN Hi-Z 0 X X OPEN OPEN OPEN Hi-Z † Output depends on AVCC AVCC CONTROL SIGNALS INTERNAL SWITCH SETTINGS O
PAGE 17
SLVS282B − SEPTEMBER 2000 − REVISED JULY 2005 APPLICATION INFORMATION 3.3 V or 5 V R1 10 kΩ ENABLE (see Note A) C1 33 µF, 20 V TPS6734 1 VCC EN + 2 REF 3 SS FB 8 L1 18 µH 7 U1 OUT 4 D1 6 TPS2211A AVCC C5 5 COMP 12 V GND AVCC AVCC + 33 µF, 20 V C2 0.01 µF 12 V 0.1 µF C4 0.001 µF AVPP 0.1 µF 5V 0.1 µF 3.3 V 0.1 µF + + 5V 10 µF 10 µF 5V 3.3 V VCCD0 3.
PAGE 18
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
PAGE 20
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS2211AIDBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 TPS2211APWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 TPS2211APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.
PAGE 21
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2211AIDBR SSOP DB 16 2000 367.0 367.0 38.0 TPS2211APWPR HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS2211APWR TSSOP PW 20 2000 367.0 367.0 38.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.