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  

   

   

SLVS317 − MAY 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

features

D Fully Integrated V

and V

Switching for

3.3 V, 5 V, and 12 V (no 12 V on TPS2223)

D Meets Current PC Cardt Standards

D V

Output Selection Independent of V

D 12-V and 5-V Supplies Can Be Disabled

D TTL-Logic Compatible Inputs

D Short-Circuit and Thermal Protection

D 24-Pin HTSSOP, 24- or 30-Pin SSOP

D 140-µA (Typical) Quiescent Current from

3.3-V Input

D Break-Before-Make Switching

D Power-On Reset

D −40°C to 85°C Operating Ambient

Temperature Range

applications

D Notebook and Desktop Computers

D Bar Code Scanners

D Digital Cameras

D Set-Top Boxes

D PDAs

description

The TPS2223, TPS2224 and TPS2226 Card-

Bus power-interface switches provide an

integrated power-management solution for two

PC Card sockets. These devices allow the

controlled distribution of 3.3 V, 5 V, and 12 V to

each card slot. The current-limiting and thermal-protection features eliminate the need for fuses. Current-limit

reporting helps the user isolate a system fault. The switch r

DS(on)

and current-limit values have been set for the

peak and average current requirements stated in the PC Card specification, and optimized for cost.

Like the TPS2214 and TPS2214A and the TPS2216 and TPS2216A, this family of devices supports

independent VPP/VCC switching; however, the standby and interface-mode pins are not supported. Shutdown

mode is now supported independently on SHDN

as well as in the serial interface. Optimized for lower power

implementation, the TPS2223 does not support 12-V switching to VPP. See the available options table for

pin-compatible device information.

AVAILABLE OPTIONS

PACKAGED DEVICES

PLASTIC SMALL OUTLINE

PowerPAD PLASTIC

SMALL OUTLINE

DB-24 DB-30

SMALL OUTLINE

(PWP-24)

†

−40°C to

TPS2223DB, TPS2224DB TPS2226DB

TPS2223PWP,

−40°C to

85°C

Pin compatibles TPS2214, TPS2214A Pin compatibles

TPS2216, TPS2216A,

TPS2206

TPS2223PWP,

TPS2224PWP

†

The DB and PWP packages are also available taped and reeled. Add R suffix to device type (e.g., TPS2223PWPR) for taped and reeled.

  ! " #$%! "  &$'(#! )!%*

)$#!" # ! "&%##!" &% !+% !%"  %," "!$%!"

"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%

!%"!/  (( &%!%"*

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

CardBus and PC Card are trademarks of PCMCIA (Personal Computer Memory Card International Association).

TPS2223, TPS2224

DB OR PWP PACKAGE

(TOP VIEW)

DATA

CLOCK

LATCH

12V

†

AVPP

AVCC

GND

RESET

SHDN

12V

†

BVPP

BVCC

3.3V

−

internal

connection

†

Pin 7 and 20 are NC for TPS2223.

Summary of content (33 pages)

PAGE 1
SLVS317 − MAY 2001 features applications D Fully Integrated VCC and Vpp Switching for D D D D D D D D D D D D D D D 3.3 V, 5 V, and 12 V (no 12 V on TPS2223) Meets Current PC Cardt Standards Vpp Output Selection Independent of VCC 12-V and 5-V Supplies Can Be Disabled TTL-Logic Compatible Inputs Short-Circuit and Thermal Protection 24-Pin HTSSOP, 24- or 30-Pin SSOP 140-µA (Typical) Quiescent Current from 3.
PAGE 2
SLVS317 − MAY 2001 TPS2226 DB PACKAGE (TOP VIEW) 5V 5V DATA CLOCK LATCH NC 12V AVPP AVCC AVCC AVCC GND NC RESET 3.3V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 5V NC NC NC NC SHDN 12V BVPP BVCC BVCC BVCC NC OC 3.3V 3.3V 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NC − No internal connection functional block diagram† Power Inputs 5V 13 S2 14 S5 1 5V 2 5V 5 V 24 S3 3.3 V 3.
PAGE 3
SLVS317 − MAY 2001 Terminal Functions TERMINAL NO. NAME I/O DESCRIPTION TPS2223 TPS2224 TPS2226 3.3V 13, 14 13, 14 15, 16, 17 I 3.3-V input for card power and chip power 5V 1, 2, 24 1, 2, 24 1, 2, 30 I 5-V input for card power 12V NA 7, 20 7, 24 I 12-V input for card power (xVPP). The two 12-V pins must be externally connected. AVCC 9, 10 9, 10 9, 10, 11 O Switched output that delivers 3.
PAGE 4
SLVS317 − MAY 2001 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Input voltage range for card power: VI(3.3V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 5.5 V VI(5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 5.5 V VI(12V)‡ . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
SLVS317 − MAY 2001 electrical characteristics, TJ = 25°C, VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V (not applicable for TPS2223), all outputs unloaded (unless otherwise noted) power switch TEST CONDITIONS† PARAMETER rDS(on) Static drain-source on-state resistance Output discharge resistance IOS 3.
PAGE 6
SLVS317 − MAY 2001 electrical characteristics, TJ = 25°C, VI(5V) = 5 V, VI(3.3V) = 3.3 V, VI(12V) = 12 V (not applicable for TPS2223), all outputs unloaded (unless otherwise noted) (continued) logic section (CLOCK, DATA, LATCH, RESET, SHDN, OC) PARAMETER TEST CONDITIONS RESET = 5.5 V II(/RESET) (see Note 2) RESET = 0 V SHDN = 5.
PAGE 7
SLVS317 − MAY 2001 switching characteristics, VCC = 5 V, TA = 25°C, VI(3.3V) = 3.3 V, VI(5V) = 5 V, VI(12) = 12 V (not applicable for TPS2223) all outputs unloaded (unless otherwise noted) PARAMETER† tr tf Output rise times (see Note 1) Output fall times (see Note 1) CL(xVCC)= 0.1 µF, CL(xVPP)= 0.1 µF, IO(xVCC) = 0 A, IO(xVPP) = 0 A CL(xVCC)= 150 µF, CL(xVPP)= 10 µF, IO(xVCC) = 0.
PAGE 8
SLVS317 − MAY 2001 PARAMETER MEASUREMENT INFORMATION xVPP xVCC IO(xVPP) IO(xVCC) LOAD CIRCUIT (xVPP) LATCH LOAD CIRCUIT (xVCC) VDD 50% LATCH VDD 50% GND tpd(on) GND tpd(off) VI(12V/5V/3.3V) 90% VO(xVPP) tpd(on) Propagation Delay (xVCC) tf tr VI(12V/5V/3.3V) VO(xVCC) 90% GND VI(5V/3.
PAGE 9
SLVS317 − MAY 2001 PARAMETER MEASUREMENT INFORMATION DATA D10 D9 D8 D6 D7 Data Setup Time D5 D4 D3 Data Hold Time D2 D1 D0 Latch Delay Time LATCH Clock Delay Time CLOCK NOTE: Data is clocked in on the positive edge of the clock. The positive edge of the latch signal should occur before the next positive edge of the clock. For definition of D0 to D10, see the control logic table. Figure 2.
PAGE 10
SLVS317 − MAY 2001 PARAMETER MEASUREMENT INFORMATION VO(/OC) 2 V/div VO(/OC) 2 V/div IO(VCC) 5 A/div IO(xVPP) 2 A/div 0 100 200 300 400 500 0 3 4 5 Figure 3. Short-Circuit Response, Short Applied to Powered-on 5-V xVCC-Switch Output Figure 4.
PAGE 11
SLVS317 − MAY 2001 PARAMETER MEASUREMENT INFORMATION TURNOFF PROPAGATION DELAY TIME, xVCC vs JUNCTION TEMPERATURE 0.8 xVCC = 5 V IO = 0.75 A CL = 150 µF 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 −50 −20 10 40 70 TJ − Junction Temperature − °C 100 t pd(off) − Turnoff Propagation Delay Time, xVCC − ms t pd(on)− Turnon Propagation Delay Time, xVCC − ms TURNON PROPAGATION DELAY TIME, xVCC vs JUNCTION TEMPERATURE 2.
PAGE 12
SLVS317 − MAY 2001 t pd(on)− Turnon Propagation Delay Time, xVCC − ms TURNON PROPAGATION DELAY TIME, xVCC vs LOAD CAPACITANCE 0.7 xVCC = 5 V IO = 0.75 A TJ = 25°C 0.6 0.5 0.4 0.3 0.2 0.1 0 0.1 1 10 100 CL − Load Capacitance − µF 1000 t pd(off) − Turnoff Propagation Delay Time, xVCC − ms PARAMETER MEASUREMENT INFORMATION TURNOFF PROPAGATION DELAY TIME, xVCC vs LOAD CAPACITANCE 2.55 2.5 xVCC = 5 V IO = 0.
PAGE 13
SLVS317 − MAY 2001 PARAMETER MEASUREMENT INFORMATION FALL TIME, xVCC vs JUNCTION TEMPERATURE RISE TIME, xVCC vs JUNCTION TEMPERATURE 1.22 2.41 xVCC = 5 V IO = 0.75 A CL = 150 µF 1.18 2.4 t f − Fall Time xVCC − ms t r − Rise Time, xVCC − ms 1.2 1.16 1.14 1.12 1.1 xVCC = 5 V IO = 0.75 A CL 150 µF 2.39 2.38 2.37 2.36 1.08 2.35 1.06 1.04 −50 −20 10 40 70 TJ − Junction Temperature − °C 2.
PAGE 14
SLVS317 − MAY 2001 PARAMETER MEASUREMENT INFORMATION FALL TIME, xVCC vs LOAD CAPACITANCE RISE TIME, xVCC vs LOAD CAPACITANCE 1.2 2.5 t f − Fall Time xVCC − ms t r − Rise Time, xVCC − ms 1 0.8 0.6 0.4 xVCC = 5 V IO = 0.75 A TJ = 25°C 0.2 0 0.1 1 10 100 CL − Load Capacitance − µF xVCC = 5 V IO = 0.75 A TJ = 25°C 2 1.5 1 0.5 0 0.
PAGE 15
SLVS317 − MAY 2001 TYPICAL CHARACTERISTICS Table of Graphs FIGURE Input current, xVCC = 3.3 V 23 Input current, xVCC = 5 V II vs Junction temperature 25 Static drain-source on-state resistance, 3.
PAGE 16
SLVS317 − MAY 2001 TYPICAL CHARACTERISTICS STATIC DRAIN-SOURCE ON-STATE RESISTANCE, 3.3 V TO xVCC SWITCH vs JUNCTION TEMPERATURE rDS(on) − Static Drain-Source On-State Resistance, 3.3 V to VCC Switch − Ω INPUT CURRENT, xVPP = 12 V vs JUNCTION TEMPERATURE I I − Input Current, xVPP = 12 V − µ A 120 100 80 60 40 20 0 −50 −20 10 40 70 TJ − Junction Temperature − °C 100 0.12 0.1 0.08 0.06 0.04 0.
PAGE 17
SLVS317 − MAY 2001 TYPICAL CHARACTERISTICS xVCC SWITCH VOLTAGE DROP, 5-V INPUT vs LOAD CURRENT xVCC SWITCH VOLTAGE DROP, 3.3-V INPUT vs LOAD CURRENT 0.14 0.1 VO− xVCC Switch Voltage Drop, 5-V Input − V VO− xVCC Switch Voltage Drop, 3.3-V Input − V 0.12 TJ = 100°C 0.08 TJ = 0°C TJ = 25°C 0.06 TJ = −40°C 0.04 TJ = 85°C 0.02 0 0 0.2 0.4 0.6 IL − Load Current − A 0.8 0.12 TJ = 0°C 0.08 TJ = 25°C 0.
PAGE 18
SLVS317 − MAY 2001 TYPICAL CHARACTERISTICS 1.435 1.43 1.425 1.42 1.415 1.41 1.405 1.4 1.395 1.39 1.385 −50 SHORT-CIRCUIT CURRENT LIMIT, 12 V TO xVPP vs JUNCTION TEMPERATURE I OS − Short-Circuit Current Limit, 12 V to xVPP − A I OS − Short-Circuit Current Limit, 5 V to xVCC − A SHORT-CIRCUIT CURRENT LIMIT, 5 V TO xVCC vs JUNCTION TEMPERATURE −20 10 40 70 TJ − Junction Temperature − °C 100 0.208 0.206 0.204 0.
PAGE 19
SLVS317 − MAY 2001 APPLICATION INFORMATION overview PC Cards were initially introduced as a means to add flash memory to portable computers. The idea of add-in cards quickly took hold, and modems, wireless LANs, global positioning satellite System (GPS), multimedia, and hard-disk versions were soon available.
PAGE 20
SLVS317 − MAY 2001 APPLICATION INFORMATION overcurrent and overtemperature protection PC Cards are inherently subject to damage that can result from mishandling. Host systems require protection against short-circuited cards that could lead to power-supply or PCB trace damage.
PAGE 21
SLVS317 − MAY 2001 APPLICATION INFORMATION shutdown mode In the shutdown mode, which can be controlled by SHDN or bit D8 of the input serial DATA word, each of the xVCC and xVPP outputs is forced to a high-impedance state. In this mode, the chip quiescent current is reduced to 1 µA or less to conserve battery power. power-supply considerations These switches have multiple pins for each 3.
PAGE 22
SLVS317 − MAY 2001 APPLICATION INFORMATION logic inputs and outputs The serial interface consists of DATA, CLOCK, and LATCH leads. The data is clocked in on the positive edge of the clock (see Figure 2). The 11-bit (D0−D10) serial data word is loaded during the positive edge of the latch signal. The positive edge of the latch signal should occur before the next positive edge of the clock occurs.
PAGE 23
SLVS317 − MAY 2001 APPLICATION INFORMATION ESD protections (see Figure 35) All inputs and outputs of these devices incorporate ESD-protection circuitry designed to withstand a 2-kV human-body-model discharge as defined in MIL-STD-883C, Method 3015. The xVCC and xVPP outputs can be exposed to potentially higher discharges from the external environment through the PC Card connector. Bypassing the outputs with 0.
PAGE 24
SLVS317 − MAY 2001 APPLICATION INFORMATION 12-V flash memory supply The TPS6734 is a fixed 12-V output boost converter capable of delivering 120 mA from inputs as low as 2.7 V. The device is pin-for-pin compatible with the MAX734 regulator and offers the following advantages: lower supply current, wider operating input-voltage range, and higher output currents.
PAGE 25
PACKAGE OPTION ADDENDUM www.ti.
PAGE 26
PACKAGE OPTION ADDENDUM www.ti.com 5-Oct-2007 TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PAGE 27
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 12.0 16.0 Q1 TPS2223DBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 TPS2223PWPR HTSSOP PWP 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 TPS2224DBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.
PAGE 28
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2223DBR SSOP DB 24 2000 367.0 367.0 38.0 TPS2223PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 TPS2224DBR SSOP DB 24 2000 367.0 367.0 38.0 TPS2224PWPR HTSSOP PWP 24 2000 367.0 367.0 38.0 TPS2226DBR SSOP DB 30 2000 367.0 367.0 38.
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PAGE 32
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 33
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.