Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - hot swap controller -48 V SOIC 14 Surface-mount

LOAD

RAMP

FLT

TPS2350

RTN

GAT

SENSE

SOURCE

GATA

GATB

–VINB–VINARAMPFLTTIM

–VINB

–VINA

5 6 14 13

FLT

Power Good

Fault

SENSE

0.01

(A)

TPS2350

www.ti.com

SLUS574D –JULY 2003–REVISED OCTOBER 2013

Hot Swap Power Manager for Redundant –48-V Supplies

Check for Samples: TPS2350

FEATURES

DESCRIPTION

• Replaces OR-ing Diodes

The TPS2350 is a hot swap power manager

• Operating Supply Range of –12 V to –80 V

optimized for replacing OR-ing diodes in redundant

• Withstands Transients to –100 V

power –48-V systems. The TPS2350 operates with

supply voltages from –12 V to –80 V, and withstands

• Programmable Current Limit

spikes to –100 V.

• Programmable Linear Inrush Slew Rate

The TPS2350 uses two power FETs as low voltage

• Programmable UV/OV Thresholds

drop diodes to efficiently select between two

• Programmable UV and OV Hysteresis

redundant power supplies. This minimizes system

• Fault Timer to Eliminate Nuisance Trips

power dissipation and also minimizes voltage drop

through the power management chain.

• Power Good and Fault Outputs

• 14-Pin SOIC and TSSOP Package

The TPS2350 also uses a third power FET to provide

load current slew rate control and peak current

limiting that is programmed by one resistor and one

APPLICATIONS

capacitor. The device also provides a power good

• –48-V Distributed Power Systems

output to enable down-stream power converters and

• Central Office Switching

a fault output to indicate load problems.

• ONET

• Base Stations

TYPICAL APPLICATION DIAGRAM

A. D1 optional per application requirements.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (27 pages)

PAGE 1
TPS2350 www.ti.
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TPS2350 SLUS574D – JULY 2003 – REVISED OCTOBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature (unless otherwise noted) (1) VALUE Input voltage range, RTN (2) UNIT –0.
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TPS2350 www.ti.com SLUS574D – JULY 2003 – REVISED OCTOBER 2013 THERMAL INFORMATION TPS2350 THERMAL METRIC (1) D (14 PINS) PW (14 PINS) θJA Junction-to-ambient thermal resistance 95.9 120.8 θJB Junction-to-board thermal resistance 51.5 62.8 θJCtop Junction-to-case (top) thermal resistance 50.7 n/a ψJT Junction-to-top characterization parameter 8.3 1 ψJB Junction-to-board characterization parameter 51.1 56.
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TPS2350 SLUS574D – JULY 2003 – REVISED OCTOBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) –VINA = –48 V, –VINB = 0 V, UV = 2.5 V, OV = 0.
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TPS2350 www.ti.com SLUS574D – JULY 2003 – REVISED OCTOBER 2013 PIN FUNCTIONS PIN NAME NO. I/O DESCRIPTION FLT 2 O Open-drain, active-low indication that the part is in fault. FLTTIM 5 I/O Connection for user programming of the fault timeout period. GAT 11 O Gate drive for external N-channel FET that ramps load current and disconnects in the event of a fault. GATA 9 O Gate drive for external N-channel FET that selects –VINA.
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TPS2350 SLUS574D – JULY 2003 – REVISED OCTOBER 2013 www.ti.com GATB: Gate drive for an external N-channel power MOSFET to select –VINB. When –VINB is more negative than –VINA, GATB is pulled 14 V above –VINB, turning on the –VINB power FET. When –VINA is more negative than –VINB, GATB is pulled down to –VINA, turning off the –VINB power FET. PG: Open-drain, active-high indication that load current is below the commanded current and the power FET is fully enhanced.
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TPS2350 www.ti.com SLUS574D – JULY 2003 – REVISED OCTOBER 2013 TYPICAL CHARACTERISTICS SUPPLY SELECTOR THRESHOLD VOLTAGE vs AMBIENT TEMPERATURE, −VINA FALLING SUPPLY SELECTOR THRESHOLD VOLTAGE vs AMBIENT TEMPERATURE, −VINB FALLING –0.350 –0.350 V(RTN) = 0 V Relative to –VINA V(–VINB) = –48 V –0.375 V(–VINB) = –20 V –0.400 V(–VINB) = –80 V –0.425 –0.450 –40 –15 10 35 60 85 VTHB – Threshold Voltage – V VTHA – Threshold Voltage – V V(RTN) = 0 V Relative to –VINB –0.
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TPS2350 SLUS574D – JULY 2003 – REVISED OCTOBER 2013 www.ti.
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TPS2350 www.ti.com SLUS574D – JULY 2003 – REVISED OCTOBER 2013 TYPICAL CHARACTERISTICS GAT HIGH-LEVEL OUTPUT VOLTAGE vs AMBIENT TEMPERATURE RAMP OUTPUT CURRENT vs AMBIENT TEMPERATURE, REDUCED RATE MODE –460 16 V(–VINA) = –48 V VOH – Output Voltage – V 12 ISRC1 – RAMP Output Current – nA V(RTN) = V(–VINB) = 0 V VOUT(RAMP) – VIN(SOURCE) = 0.
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TPS2350 SLUS574D – JULY 2003 – REVISED OCTOBER 2013 www.ti.com TYPICAL CHARACTERISTICS TIMER DISCHARGE CURRENT vs AMBIENT TEMPERATURE FAULT LATCH THRESHOLD VOLTAGE vs AMBIENT TEMPERATURE 0.50 V(RTN) = V(–VINB) = 0 V V(–VINA) = –48 V Relative to SOURCE VFLT – Fault Latch Threshold – V IDSG – Discharge Current – mA 0.45 4.25 V(RTN) = V(–VINB) = 0 V –80 V ≤ V(–VINA) ≤ –20 V VOUT(FLTTIM) – VIN(SOURCE) =2V 0.40 0.35 0.30 0.25 0.20 –40 –15 10 35 60 85 4.15 4.05 3.95 3.85 3.
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TPS2350 www.ti.com SLUS574D – JULY 2003 – REVISED OCTOBER 2013 FUNCTIONAL BLOCK DIAGRAM RTN 1 UV Input UV Comparator + 3 1.4 V Input OV Comparator OV Disable 4 1.
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TPS2350 SLUS574D – JULY 2003 – REVISED OCTOBER 2013 www.ti.com APPLICATION INFORMATION Supply Section The supply selection comparator selects between –VINA and –VINB based on which supply has a larger magnitude. To prevent chattering between two nearly identical supplies, the supply selection comparator has 400 mV of hysteresis. This prevents supply noise or ripple from tripping the comparator and should be adequate for most systems.
PAGE 13
TPS2350 www.ti.com SLUS574D – JULY 2003 – REVISED OCTOBER 2013 APPLICATION INFORMATION Setting the Sense Resistor Value Due to the current-limiting action of the internal LCA, the maximum allowable load current for an implementation is easily programmed by selecting the appropriate sense resistor value. The LCA acts to limit the sense voltage VSENSE to its internal reference. Once the voltage at the RAMP pin exceeds approximately 4 V, this limit is the clamp voltage, VREF_K.
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TPS2350 SLUS574D – JULY 2003 – REVISED OCTOBER 2013 www.ti.com APPLICATION INFORMATION Setting the Fault Timing Capacitor The fault timeout period is established by the value of the capacitor connected to the FLTTIM pin, CFLT. The timeout period permits riding out spurious current glitches and surges that may occur during operation of the system, and prevents indefinite sourcing into faulted loads.
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TPS2350 www.ti.com SLUS574D – JULY 2003 – REVISED OCTOBER 2013 APPLICATION INFORMATION If the result of Equation 4 is larger than the maximum input supply value, then the load can be expected to charge completely during the inrush slewing portion of the insertion event. However, if this voltage is less than the maximum supply input, VIN(MAX), the HSPM transitions to the constant-current charging of the load. The remaining amount of time required at IMAX is determined from Equation 5.
PAGE 16
TPS2350 SLUS574D – JULY 2003 – REVISED OCTOBER 2013 www.ti.com APPLICATION INFORMATION Setting the Undervoltage and Overvoltage Thresholds The UV and OV pins can be used to set the undervoltage (VUV) and overvoltage (VOV) thresholds of the hot swap circuit. When the input supply is below VUV or above VOV, the GAT pin is held low, disconnecting power from the load, and the PG output is deasserted.
PAGE 17
TPS2350 www.ti.com SLUS574D – JULY 2003 – REVISED OCTOBER 2013 APPLICATION INFORMATION For example, assume the typical application design targets have been set to undervoltage turn-on at 33 V (input supply rising), turn-off at 31 V (input voltage falling), and overvoltage shutdown at 72 V. Then Equation 9 yields R1 = 200 kΩ for the 2-V hysteresis. Once the value of R1 is selected, it is used to calculate resistors R2 and R3. é ù 1.4 ´ R1 VUV_L R2 = ´ ê1– ú –5 (VUV_L -1.4) ë (VOV_L + 10 ´ R1)û (10) 1.
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TPS2350 SLUS574D – JULY 2003 – REVISED OCTOBER 2013 www.ti.com REVISION HISTORY Changes from Revision B (December 2005) to Revision C • Replaced the Dissipations Rating table with the Thermal Information table ........................................................................ 3 Changes from Revision C (March 2011) to Revision D • 18 Page Page Changed the FUNCTIONAL BLOCK DIAGRAM - Power Good Detection terminals were reversed .................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 7-Oct-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS2350DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TPS2350PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2350DR SOIC D 14 2500 367.0 367.0 38.0 TPS2350PWR TSSOP PW 14 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.