TPS2359 www.ti.com SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 Full-Featured, Dual-Slot AdvancedMC™ Controller Check for Samples: TPS2359 FEATURES APPLICATIONS • • • • • • • • • • • • 1 2 • • • ATCA AdvancedMC™ Compliant Full Control for Two AdvancedMC™ Modules Independent 12-V Current Limit and Fast Trip 3.3-V and 12-V FET ORing for MicroTCA™ Internal 3.
TPS2359 SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 www.ti.com ORDERING INFORMATION (1) (2) (1) DEVICE TEMPERATURE PACKAGE (2) ORDERING INFORMATION TPS2359 -40°C to 85°C QFN36 TPS2359RHH Add an R suffix to the device type for tape and reel. For the most current package and ordering information see the Package Option Addendum at the end of this document or see the TI Web site at www.ti.com.
TPS2359 www.ti.com SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 ELECTRICAL CHARACTERISTICS IN3A = IN3B = VDD3A = VDD3B = 3.3 V. IN12A = IN12B = SENPA = SENPB = SENMA = SENMB = SETPA = SETPB = 12 V. EN3A = EN3B = AGND = GNDA = GNDB = 0 V. SUM12A = SUM12B = 6.8 kΩ to ground. SUM3A = SUM3B = 3.3 kΩ to ground. All other pins open. All I2C bits at default values. Over free air temperature operating range and all voltages referenced to AGND, -40°C ≤ TA ≤ 85°C, unless otherwise noted.
TPS2359 SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) IN3A = IN3B = VDD3A = VDD3B = 3.3 V. IN12A = IN12B = SENPA = SENPB = SENMA = SENMB = SETPA = SETPB = 12 V. EN3A = EN3B = AGND = GNDA = GNDB = 0 V. SUM12A = SUM12B = 6.8 kΩ to ground. SUM3A = SUM3B = 3.3 kΩ to ground. All other pins open. All I2C bits at default values. Over free air temperature operating range and all voltages referenced to AGND, -40°C ≤ TA ≤ 85°C, unless otherwise noted.
TPS2359 www.ti.com SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 ELECTRICAL CHARACTERISTICS (continued) IN3A = IN3B = VDD3A = VDD3B = 3.3 V. IN12A = IN12B = SENPA = SENPB = SENMA = SENMB = SETPA = SETPB = 12 V. EN3A = EN3B = AGND = GNDA = GNDB = 0 V. SUM12A = SUM12B = 6.8 kΩ to ground. SUM3A = SUM3B = 3.3 kΩ to ground. All other pins open. All I2C bits at default values. Over free air temperature operating range and all voltages referenced to AGND, -40°C ≤ TA ≤ 85°C, unless otherwise noted.
TPS2359 SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 www.ti.com DEVICE INFORMATION TPS2359 BLOCK DIAGRAMS R SENSE R SET SENPx SENMx SETx 100 100 PASSx BLKx OUT12x pgat\ 12dis 100 mv + Q Pump ~25 V 30 uA ogat 10 us + IN12x 30 uA 10 us Fault Timer Vcp Vcp 12dis FLT12x\ EN12x\ PG3\ RSUM 6800 W 675 mV x (12xCL/1111) + DCC R1/4[7] SUM12x 60 mA 10 mv + -3 mv OUT12x + R Q S Q ogat OUT 100 us + pgat\ oren vpg PG12x\ Figure 3.
TPS2359 www.ti.com SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 Management Power Channel (two channels per device) 0.1 W IN3 OUT3 2.8 V + gat 96 W VDD3 en 30 mv 30 us + Q Pump 2 PG\ to I C 30 uA + vcp ~25 v 12dis Fault Timer vcp 30 us FLT \ to I 2 C Control from I 2 C SUM3 3300 + en EN3 vthoc - [ 675 mv nominal ] 3ORON 10 mv + -3 mv OUT3 R Q S Q gat + Common Circuitry IN12A VINT en por IN12B IN3A PREREG IN3B POR 2.
TPS2359 SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 www.ti.
TPS2359 www.ti.
TPS2359 SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 www.ti.com DETAILED PIN DESCRIPTION A0, A1, A2 These three pins select one of 27 unique I2C addresses for address of the TPS2359. Each pin may be tied to ground, tied to the VINT pin, or left open. See TPS2359 I2C Interface section for details and Table 17 for specific addresses. AGND Ground pin for analog circuitry inside the TPS2359. BLKx Gate drive pin for the 12x channel BLK FET. This pin sources 30 μA to turn the FET on.
TPS2359 www.ti.com SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 TYPICAL CHARACTERISTICS IDD at 25°C vs 12-V VDD 3-V CHANNEL ORING TURN-ON THRESHOLD 12 2.45 2.40 11 IDD - mA mV 2.35 10 9 2.30 2.25 2.20 2.15 8 -50 0 50 100 2.10 150 -50 TJ - Temperature - °C 0 50 100 150 VDD - 25°C Figure 4. Figure 5. 12-V CURRENT LIMIT THRESHOLD 3-V CHANNEL ORING TURN-OFF THRESHOLD 51.0 -1.0 50.8 -2.0 50.6 mV mV 0.0 -3.0 50.4 -4.0 50.2 50.0 -5.
TPS2359 SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 3-V IDD vs TEMPERATURE 12-V CHANNEL ORING TURN-OFF THRESHOLD 0.0 0.26 -1.0 0.25 -2.0 mV IDD - mA 0.24 0.23 -3.0 0.22 -4.0 0.21 -5.0 0.20 -50 -50 0 50 100 0 150 50 100 150 TJ - Temperature - °C TJ - Temperature - °C Figure 8. Figure 9. 12-V CURRENT (mA) vs TEMPERATURE 12-V CHANNEL ORING TURN-ON THRESHOLD 12.0 2.4 11.5 11.0 2.3 mV Current - mA 10.5 10.0 2.2 6 9.5 9.0 2.1 8.
TPS2359 www.ti.com SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 TYPICAL CHARACTERISTICS (continued) Figure 12. OUT3A Startup Into 22-Ω (150 mA) 150-μF Load Figure 13. OUT3A Load Stepped from 165 mA to 240 mA Figure 14. OUT3A Short Circuit Under Full Load (165 mA) Zoom View Figure 15.
TPS2359 SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 14 Figure 16. OUT3A Startup Into Short Circuit Figure 17. OUT12A Startup Into 500-Ω, 830-μF Load Figure 18. OUT12A Startup Into 80-Watt, 830-μF Load Figure 19. OUT12A Short Circuit Under Full Load (6.
TPS2359 www.ti.com SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 TYPICAL CHARACTERISTICS (continued) Figure 20. OUT12A Short Circuit Under Full Load (6.7 A) Zoom View Figure 21. OUT12A Startup Into Short Circuit Figure 22. OUT12A Overloaded While Supplying 6.
TPS2359 SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 www.ti.com REFERENCE INFORMATION The TPS2359 has been designed to simplify compliance with the PICMG-AMC.R2.0 and PICMG-MTCA.0 specifications. These specifications were developed by the PCI Industrial Computer Manufacturers Group (PICMG). These two specifications are derivations of the PICMG-ATCA (Advanced Telecommunication Computing Architecture) specification originally released in December, 2002.
TPS2359 www.ti.com SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 Summary of Registers Table 2. Summary of Registers BIT NAME DEFAULT DESCRIPTION Register 0 Read/Write channel 12A configuration 0 12ACL0 1 Clearing bit reduces 12A current limit and fast threshold by 5%. 1 12ACL1 1 Clearing bit reduces 12A current limit and fast threshold by 10%. 2 12ACL2 1 Clearing bit reduces 12A current limit and fast threshold by 20%.
TPS2359 SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 www.ti.com Table 2. Summary of Registers (continued) BIT NAME DEFAULT 0 3BFT0 1 Setting bit increases 3B fault time by 0.45 ms. DESCRIPTION 1 3BFT1 0 Setting bit increases 3B fault time by 0.9 ms. 2 3BFT2 0 Setting bit increases 3B fault time by 1.8 ms. 3 3BFT3 0 Setting bit increases 3B fault time by 3.6 ms. 4 3BFT4 0 Setting bit increases 3B fault time by 7.2 ms. 5 3BEN 0 Clearing bit disables 3B.
TPS2359 www.ti.com SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 Detailed Description of Registers Register 0 Table 3. Register 0: Channel 12A Configuration (Read/Write) BIT NAME DEFAULT 0 12ACL0 1 Clearing bit reduces 12A current limit and fast threshold by 5%. DESCRIPTION 1 12ACL1 1 Clearing bit reduces 12A current limit and fast threshold by 10%. 2 12ACL2 1 Clearing bit reduces 12A current limit and fast threshold by 20%.
TPS2359 SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 www.ti.com Register 1 Table 4. Register 1: Channel 12A Configuration (Read/Write) BIT NAME DEFAULT 0 12AFT0 1 Setting bit increases 12A fault time by 0.45 ms. DESCRIPTION 1 12AFT1 0 Setting bit increases 12A fault time by 0.9 ms. 2 12AFT2 0 Setting bit increases 12A fault time by 1.8 ms. 3 12AFT3 0 Setting bit increases 12A fault time by 3.6 ms. 4 12AFT4 0 Setting bit increases 12A fault time by 7.2 ms.
TPS2359 www.ti.com SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 Register 2 Table 5. Register 2: Channel 3A Configuration (Read/Write) BIT NAME DEFAULT 0 3AFT0 1 Setting bit increases 3A fault time by 0.45 ms. DESCRIPTION 1 3AFT1 0 Setting bit increases 3A fault time by 0.9 ms. 2 3AFT2 0 Setting bit increases 3A fault time by 1.8 ms. 3 3AFT3 0 Setting bit increases 3A fault time by 3.6 ms. 4 3AFT4 0 Setting bit increases 3A fault time by 7.2 ms. 5 3AEN 0 Clearing bit disables 3A.
TPS2359 SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 www.ti.com Register 3 Table 6. Register 3: Channel 12B Configuration (Read/Write) BIT NAME DEFAULT DESCRIPTION 0 12BCL0 1 Clearing bit reduces 12B current limit and fast threshold by 5%. 1 12BCL1 1 Clearing bit reduces 12B current limit and fast threshold by 10%. 2 12BCL2 1 Clearing bit reduces 12B current limit and fast threshold by 20%. 3 12BCL3 1 Clearing bit reduces 12B current limit and fast threshold by 40%.
TPS2359 www.ti.com SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 Register 4 Table 7. Register 4: Channel 12B Configuration (Read/Write) BIT NAME DEFAULT 0 12BFT0 1 Setting bit increases 12B fault time by 0.45 ms. DESCRIPTION 1 12BFT1 0 Setting bit increases 12B fault time by 0.9 ms. 2 12BFT2 0 Setting bit increases 12B fault time by 1.8 ms. 3 12BFT3 0 Setting bit increases 12B fault time by 3.6 ms. 4 12BFT4 0 Setting bit increases 12B fault time by 7.2 ms.
TPS2359 SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 www.ti.com Register 5 Table 8. Register 5: Channel 3B Configuration (Read/Write) BIT NAME DEFAULT 0 3BFT0 1 Setting bit increases 3B fault time by 0.45 ms. DESCRIPTION 1 3BFT1 0 Setting bit increases 3B fault time by 0.9 ms. 2 3BFT2 0 Setting bit increases 3B fault time by 1.8 ms. 3 3BFT3 0 Setting bit increases 3B fault time by 3.6 ms. 4 3BFT4 0 Setting bit increases 3B fault time by 7.2 ms. 5 3BEN 0 Clearing bit disables 3B.
TPS2359 www.ti.com SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 Register 6 Table 9. Register 6: System Configuration (Read/Write) BIT NAME DEFAULT DESCRIPTION 0 PPTEST 0 12-V pulldown test pin. Asserting this pulls the PASSx and BLKx pins to 0 V. 1 FLTMODE 0 Clearing bit forces channels to latch off after over-current fault. Setting bit allows channels to automatically attempt restart after fault. 2 SPARE 0 This bit must always be set to 0.
TPS2359 SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 www.ti.com Register 7 Table 10. Register 7: Latched IRPT Channel Status Indicators (Read-only, cleared on read) BIT NAME DEFAULT 0 12APG 1 Latches high when OUT12A goes from above VTH_PG to below VTH_PG. DESCRIPTION 1 12AFLT 0 Latches high when 12A fault timer has run out. 2 3APG 1 Latches high when OUT3A goes from above VTH_PG to below VTH_PG. 3 3AFLT 0 Latches high when 3A fault timer has run out.
TPS2359 www.ti.com SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 Register 8 Table 11. Register 8: Latched Status Indicators (Read-only, cleared on read) BIT NAME DEFAULT DESCRIPTION 0 12AOC 0 Latches high when 12A enters over-current. 1 12AFTR 0 Latches high if 12A fast trip threshold exceeded. 2 3AOC 0 Latches high when 3A enters over-current. 3 3AFTR 0 Latches high if 3A fast trip threshold exceeded. 4 12BOC 0 Latches high when 12B enters over-current.
TPS2359 SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 www.ti.com Register 9 Table 12. Register 9: Unlatched Status Indicators (Read-only) BIT NAME DEFAULT DESCRIPTION 0 12ABS - High indicates BLKA commanded high. 1 12APS - Low indicates VPASSA > VOUT12A + 6 V. 2 3ABS - Low indicates IN3A > OUT3A. 3 12BBS - High indicates BLKB commanded high. 4 12BPS - Low indicates VPASSB > VOUTB + 6 V. 5 3BBS - Low indicates IN3B > OUT3B.
TPS2359 www.ti.com SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 APPLICATION INFORMATION Introduction The TPS2359 controls two 12-V power paths and two 3.3-V power paths. Each power path can draw from a single common supply, or from two independent supplies. The TPS2359 occupies a 36-pin QFN package. An I2C interface not only enables the implementation of two AdvancedMC™ slots using one small integrated circuit, but it also provides many opportunities for design customization.
TPS2359 SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 www.ti.com Fault, Power Good, Overcurrent, and FET Status Bits The TPS2359 I2C interface includes six status bits for each channel, for a total of 24 bits. These status bits occupy registers 7, 8, and 9. The following table summarizes the locations of these bits: Table 14.
TPS2359 www.ti.com SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 3.3V Current Limiting The 3.3-V management power channels include internal pass FETs and current sense resistors. The onresistance of a management channel - including pass FET, sense resistor, metallization resistance, and bond wires - typically equals 290 mΩ and never exceeds 500 mΩ. The AdvancedMC™ specification allows a total of 1 Ω between the power source and the load. The TPS2359 never consumes more than half of this budget. The 3.
TPS2359 SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 www.ti.com The recommended value of RSENSE = 5 mΩ sets the fast trip threshold at 20 A for 12xCL = 1111B. This choice of sense resistor corresponds to the maximum 19.4-A inrush current allowed by the MicroTCA™ specification. The 12-V current limit function regulates the PASSx pin voltage to prevent the current through the channel from exceeding ILIMIT. The current limit circuitry includes two amplifiers, A1 and A2, as shown in Figure 23.
TPS2359 www.ti.com SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 Redundant vs Non-Redundant Inrush Current Limiting The TPS2359 can support either redundant or non-redundant systems. Redundant systems generally use a single fixed current limit, as described above. Non-redundant systems can benefit from a higher current limit during inrush to compensate for the lack of a redundant supply. The MicroTCA™ standard allows up to 19.
TPS2359 SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 www.ti.com Example 1: Set up 12A to start into an 80 W load and charge a 1600 uF capacitor in less than 3 ms. Set an operational ILIMIT of 8.25 A +/ - 10%. First, calculate how much current is needed for capacitor charging and powering the load; ISTARTUP = ICHARGE + ILOAD = 6.4A + 6.67 A = 13.7 A Where; ICHARGE = CV/T = 1600uF x 12V / .003 s = 6.4 A ILOAD = PLOAD / VLOAD = 80 W / 12V = 6.67 A Now calculate RSET for an ILIMIT of 13.7 A.
TPS2359 www.ti.com SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 Example 2: Set up 12A to startup into an 80 W load and charge a 1600 uF at not more than 17 A nominal. Then drop to an operational ILIMIT of 8.25 A +/ 10%. ISTARTUP = 17 A First, the correct RSET must be found to set maximum ILIMIT to less than 17 A. RSET = ( ILIMIT x RSENSE x RSUM ) / 0.675 = 857 ! " ( closest 1% value = 845 ! ) Where; RSUM = 6810 ! " RSENSE = 5 m! Now ILIMIT = 0.675RSET / ( RSUM RSENSE ) = 16.
TPS2359 SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 www.ti.com Multiswap Operation in Redundant Systems TheTPS2359 features an additional mode of operation called Multiswap redundancy. This technique does not require a microcontroller, making it simpler and faster than the redundancy schemes described in the MicroTCA™ standard. Multiswap is especially attractive for AdvancedMC™ applications requiring redundancy, but need not comply with the MicroTCA™ power module standard.
TPS2359 www.ti.com SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 12-V Inrush Slew Rate Control As normally configured, the turn-on slew rate of the 12-V channel output voltage VOUT12x equals: dVout I src @ dt Cg (7) where ISRC equals the current sourced by the PASSx pin (nominally 30 μA) and Cg equals the effective gate capacitance. For purposes of this computation, one can assume that the effective gate capacitance approximately equals the reverse transfer capacitance, CRSS.
TPS2359 SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 www.ti.com 12-V ORing Operation for Redundant Systems The 12-V channels use external pass FETs to provide reverse current blocking. The TPS2359 pulls the BLKx pin high when the input-to-output differential voltage IN12x-OUT12x exceeds a nominal value of 10 mV, and it pulls the pin low when this differential falls below a nominal value of -3 mV. These thresholds provide a nominal 13 mV of hysteresis to help prevent false triggering.
TPS2359 www.ti.com SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 Internal Bleed-Down Resistors and Bleed-Down Thresholds The TPS2359 includes two features intended to support downstream loads that require removal and reapplication of power to properly reset their internal circuitry. Disabling and re-enabling a channel of the TPS2359 will not necessarily reset such a load because the capacitance attached to the output bus may not fully discharge.
TPS2359 SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 www.ti.com TPS2359 I2C Interface The TPS2359 digital interface meets the specifications for an I2C bus operating in the high-speed mode. One can configure the interface to recognize any one of 27 separate I2C addresses using the A0, A1, and A2 pins (Table 17 I2C Addressing). These pins accept any of three distinct voltage levels. Connecting a pin to ground generates a low level (L). Connecting a pin to VINT generates a high level (H).
TPS2359 www.ti.com SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 Data Stop Register Number Ack 0 Ack A ddress Ack Start Register Write: Figure 30 Format of a Register Writeshows the format of a register write. First the master issues a start condition, followed by a seven-bit I2C address. Next the master writes a zero to signify that it wishes to conduct a write operation. Upon receiving an acknowledge from the slave, the master writes the eight-bit register number across the bus.
TPS2359 SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 www.ti.com Using the TPS2359 to Control Two AdvancedMC™Slots The TPS2359 has been designed for use in systems under I2C control. Figure 32 shows the TPS2359 in a typical system implementing redundant power sources. A non-redundant application would omit the blocking FETs and leave the BLKx pins unconnected. CSD16406Q3 x 2 12 V in 12 V .005 AdvancedMC 422 100 1u SENPA SETA SENMA PASSA BLKA IN12A Slot A 3.
TPS2359 www.ti.com SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 Layout Consideration TPS2359 applications require careful attention to layout in order to ensure proper performance and minimize susceptibility to transients and noise. Important points to consider include: 1. Connect AGND, GNDA, and GNDB to a ground plane. 2. Place 0.01-μF or larger ceramic bypass capacitors on IN12A, IN12B, VDD3A, and VDD3B. Minimize the loop area created by the leads running to these devices. 3.
TPS2359 SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 www.ti.com Transient Protection The need for transient protection in conjunction with hot-swap controllers should always be considered. When the TPS2359 interrupts current flow, input inductance generates a positive voltage spike on the input and output inductance generates a negative voltage spike on the output.
TPS2359 www.ti.com SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 The Risk With Output Capacitors Putting transient filter capacitors at the output of a uTCA power module can cause nuisance trips when that power module is plugged into an active bus. If there is no series resistance with the capacitor and the bus is low impedance an inrush surge can cause the active supply to “detect” a short circuit and shut down.
TPS2359 SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 www.ti.com REVISION HISTORY Changes from Revision E (November 2009) to Revision F • Page Changed leakage typo in the EC table from mA to µA ......................................................................................................... 5 Changes from Revision F (August 2010) to Revision G Page • Changed Fault Timer TYP values from 1 ms, and 0.5 ms to 0.5 and 0.41. .........................................................................
TPS2359 www.ti.com SLUS792H – FEBRUARY 2008 – REVISED MAY 2013 Changes from Revision G (November 2011) to Revision H Page • Changed the Fault Timer section section of the ELECTRICAL CHARACTERISTICS table ................................................ 3 • Changed Table 2 Register 1, Register 2, Register 4, and Register 5 From: fault time by 0.41, 0.82, 1.64, 3.28, and 6.56 ms To: 0.45, 0.9, 1.8, 3.6 and 7.2 ms. .........................................................................................
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS2359RHHR VQFN RHH 36 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 TPS2359RHHT VQFN RHH 36 250 180.0 16.4 6.3 6.3 1.1 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2359RHHR VQFN RHH 36 2500 367.0 367.0 38.0 TPS2359RHHT VQFN RHH 36 250 210.0 185.0 35.
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