TPS2363 www.ti.com SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 PCIExpress Server Dual Slot Hot Plug Controller Check for Samples: TPS2363 FEATURES DESCRIPTION • • • • • • • • • The TPS2363 is a dual-slot PCIExpress hot plug controller with SMBus control and monitoring functions. There are sense resistor programmable current limits for the 3.3-V and 12-V supply.
TPS2363 SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 www.ti.com Application Diagram (continued) The TPS2363 has bleed-down circuits to discharge the module before it is removed, when the voltages are below the low comparator threshold, slot PWROFF will be set indicating it is safe to remove the module. This is available over the SMBus. Gate capacitors are used to set the rise time, this allows soft turn on of the slot avoiding power glitches.
TPS2363 www.ti.com SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 ABSOLUTE MAXIMUM RATINGS Over operating free-air temperature range (unless otherwise noted) (1) PARAMETER VALUE Supply 12 V, SH12A/B Supply 3.3 V & SH33A/B, AUXINA/B 0 to 5 Logic input/output V -0.5 to 5 VAUXA/B output voltage 0 to 5 VAUXA/B output current 1.
TPS2363 SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS Supply voltages; SH33A/B & AUXINA/B = 3.0 V to 3.6 V, SH12A/B = 10.8 V to 13.2 V, TA = -40°C to 85°C, RFILTER = open, all outputs are not loaded (unless otherwise specified). (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PCIExpress 12-V Supply Gate Controller 12-V voltage, SH12A/B 10.8 13.2 ONA/B = high, (No load) 12-V supply current, SH12A/B, per slot 1 ONA/B = low, disabled main supply 0.
TPS2363 www.ti.com SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 ELECTRICAL CHARACTERISTICS (continued) Supply voltages; SH33A/B & AUXINA/B = 3.0 V to 3.6 V, SH12A/B = 10.8 V to 13.2 V, TA = -40°C to 85°C, RFILTER = open, all outputs are not loaded (unless otherwise specified). (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PCIExpress AUX AUXINA/B voltage AUXINA/B supply current VAUXA/B on resistance Current llmit UVLO PGOOD bleed down resistance 3.0 3.
TPS2363 SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Supply voltages; SH33A/B & AUXINA/B = 3.0 V to 3.6 V, SH12A/B = 10.8 V to 13.2 V, TA = -40°C to 85°C, RFILTER = open, all outputs are not loaded (unless otherwise specified).
TPS2363 www.ti.com SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 DEVICE INFORMATION TERMINAL FUNCTIONS TERMINAL NAME TPS2363 MIC2592B NO. I/O DESCRIPTION FAULTA/B /FAULTA/B 1/36 O Active low, fault output for the slot (filtered). FAULTA/B indicates an over-current, undervoltage, or over temperature event occurred on either the AUX or the main supplies. AUXENA/B must be disabled to reset an AUX fault. ONA/B must be disabled to reset a main fault.
TPS2363 SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL NAME TPS2363 NO. MIC2592B OUT33A/B 3VOUTA/B GND GND AUXHIA/B N/C RFILTER A&B RFILTER [A&B] 16/21 I/O DESCRIPTION I/O 3.3-V channel output, used to monitor the SlotA/B voltage for power good. When the main power is turned off, there is a 1.2-kΩ pull-down, bleed-down circuit, when all the voltages are below 100 mV slot power off can be read from the SMBus.
TPS2363 www.ti.com SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 AUXINA/B VAUXA/ B + + + S 2.9V + AUX Fault Q AUX good + R Q AUXENA/B + SH12A/B 2.8V Power on reset Ref Charge pump + 12UV SH12x Hold off 9V + Inverted PMOS drive + SL12A/B 50 mV G12A/B 25 µA PON + OUT12A/B 12 fast + + POFF 100 mV + SL33A/B + 33UV PON 2.5V + 12 good + 100mV 10.
TPS2363 SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 www.ti.com REFERENCE INFORMATION PCIExpress CEM (Card Electromechanical Specification) Standard Table 1. Power Supply Rail Requirements POWER RAIL x1 CONNECTOR x4/x8 CONNECTOR x16 CONNECTOR 3.3 V Voltage tolerance ±9% (max) ±9% (max) ±9% (max) Supply current 3.0 A (max) 3.0 A (max) 3.0 A (max) Capacitive load 1000 mF (max) 1000 mF (max) 1000 mF (max) 12 V Voltage tolerance ±8% ±8% ±8% Supply current 0.5 A 2.1 A (max) 4.4 / 5.
TPS2363 www.ti.com SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 APPLICATION INFORMATION Power On Reset AUXINA/B is the logic voltage supply. When AUXINA/B voltage is greater than the under voltage lock out (UVLO) the TPS2363 will start a reset. This clears all the registers and holds off all the SlotA/B voltages. Initialization takes less than 250 µs after the voltage on AUXINA/B is above the UVLO. A power glitch on AUXINA/B causes a TPS2363 reset.
TPS2363 SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 www.ti.com System Operation The TPS2363 hot plug controller allows for insertion and removal of PCIExpress cards into a running system with the slot powered off. The switch closure when the module is inserted starts the sequence. A GPI pin can be used for the switch input. VAUXA/B is enabled turning on the 3.3-V VAUXA/B supply with the internal FET. VAUXA/B is current limited to 400 mA by default, the PCIExpress standard is 375 mA maximum.
TPS2363 www.ti.com SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 Fault Faults can occur on any of the input supplies, 3.3-V VAUX (VAUXINA/B), 3.3-V (SH33H), and 12-V (SH12A/B). These inputs are monitored for under-voltage and issue a FAULTA/B if the power segment is commanded on when it is out of range. VAUXINA/B UVLO causes a power on reset that clears the FAULTA/B. The SlotA/B voltages (hot plug output voltages) are also monitored for under-voltage.
TPS2363 SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 www.ti.com Fault Timer To avoid nuisance trips, the turn off time of the main power supplies and AUX in a normal over-current event is controlled by a fault timer. The over current comparator’s response time, tFLT, is user selectable and set by external capacitors, one for each channel. Connect the capacitor from FILTERA/B to ground.
TPS2363 www.ti.com SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 Circuit Breaker Circuit breaker control does not protect the system from glitches on a fault. The backplane and power system must be designed for a higher current level. The peak current is only limited by the RDS(on) of the power FET used for the hot plug. When a fault occurs there is no current limit, the fault timer controls when power is turned off to the module. The fault time is typically set in the 10 ms range.
TPS2363 SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 www.ti.com Fast Trip Fast trip, shown in Figure 5, normally allows twice the fault current and allows a high current fault for 100 ns, if the fault setting is 6 A the system may see 6 A to 12 A for up to the fault time which is normally around 10 ms depending on the fault capacitor selection.
TPS2363 www.ti.com SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 Selection Trade-Offs System design determines the controller’s power off characteristics. High-end never-fail systems often use the current limit function and power off the module when a fault is detected. In these systems it is important that the module have a chance to recover and the system not hang. Mid-range servers often use the circuit breakers with fast trip.
TPS2363 SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 www.ti.com Fault Threshold calculations An over-current fault is determined by the voltage developed across a sense resistor. A small resistance, typically less than tens of milliohms is placed in the slot current switch path. The voltage across the sense resistor is input to a comparator that turns on when the voltage is greater than the current limit threshold. The 3.3 V has a PCIExpress specification of 3.0 A for any connector width.
TPS2363 www.ti.com SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 Inrush Current Inrush current is the large current at start-up due to capacitive loads. It can reduce the system voltage causing problems for other operating modules in the system. High inrush currents can destroy connector pins and circuit board etch.
TPS2363 SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 www.ti.com For the 12-V output, a P-channel FET is used in order to get sufficient VGS for control. In this configuration the FET is a high-gain amplifier. The slew rate for the 12 V is controlled by a Miller capacitance from the gate of the FET to the source. The calculation is the same as the 3.3 V case but CMILLER is reduced because by the gfs of the FET. Example: • The PCIExpress specification allows for 2000 mF maximum capacitance for the 12 V.
TPS2363 www.ti.com SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 MOSFET RDS(on) An important parameter in choosing a FET is the on-resistance, RDS(on). The lower the RDS(on), the smaller the steady state power dissipation of the MOSFET and the easier to maintain the PCI recommended bus voltage. Low RDS(on) does contribute to excessive currents under short circuit conditions discussed below. The lowest RDS(on) MOSFETs are the most expensive.
TPS2363 SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 www.ti.com Reference Design Figure 7.
TPS2363 www.ti.com SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 150-W Add-In Module The PCI Express x16 Graphics 150W-ATX Specification Revision 1.0 states: • The slot connector provides main power to 75 W. • A second cable-mounted add-in-module connector is used for an additional 12 V at 75 W. • The 12-V main power at the slot and the 12-V additional power are separate. • The hot plug functionality of PCI Express CEM1.1 is not supported.
TPS2363 SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 www.ti.com Layout Considerations Since the main voltage inputs to the TPS2363 are also the sense resistor inputs, some consideration must be given to the layout for accurate read-back of the output currents. See Figure 9 and Figure 10 • Sense resistors are close to the TPS2363 • TPS2363 pins SH12A/B and SH33A/B are not connected to inner layer power. • Connect the high side sense resistor to inner layer power. • Use a 0.
TPS2363 www.ti.com SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 Over Temperature The TPS2363 has a wide operating junction temperature range and each channel operates independently. If the temperature of one slot controller increases to TSHUT1 and a normal VAUXA/B over-current condition exists, the out of range channel immediately shuts off all main and VAUXA/B power to the slot. The over-temperature shutdown does not use the fault timer and supersedes it if the timer is in process.
TPS2363 SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 www.ti.com General Purpose Input Pins The general purpose input (GPI) pins can be connected to any 3.3-V digital signal for read-back to the system controller. These inputs are switch de-bounced for direct connection to a VAUXA/B control (switch), attention or manually-operated retention latch. Each GPI pin has an internal 100-kΩ pull down. Poweroff The PWROFFA/B bits are available through the SMBus function register.
TPS2363 www.ti.com SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 Direct Mode In direct mode, the TPS2363 is controlled by AUXENA/B to enable VAUXA/B and ONA/B to enable the main supplies. FORCEONA/B can be used for test and debug. PGOODA/B and FAULTA/B is the only status available without using the SMBus. The SMBus does not have to be disabled to use direct mode. The SMBus can be used to read the status and the general purpose inputs.
TPS2363 SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 www.ti.com Echo Reset Some bits in the STATA/B and the common status register are fault indications that can cause an interrupt. These bits remain set even if the fault condition has been cleared. This is done to allow time for the controller to process the interrupt and read the fault condition. When the controller writes a 1 back to the set bit, the bit is cleared on the next read of the register if the fault condition has been removed.
TPS2363 www.ti.com SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 SMBUS Receive byte timing 1 9 1 9 SCL A6 SDA A5 A4 A3 A2 A1 A0 D7 R/W D6 D5 D4 D3 D2 D1 D0 Frame 2 Data Byte from TPS2363 Frame 1 SMBus Slave Address Byte Start by Master NACK by MASTER ACK by TPS2363 Figure 14. SMBus Receive Byte Timing Table 7.
TPS2363 SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 www.ti.com Valid Read Data: (Y corresponds any of the combinations from above) • 0Yh – VAUXA/B and main have are not in power good mode. • 4Yh – Only the main supplies are in power good mode. • 8Yh – Only the VAUXA/B is in power good mode. • cYh – Both VAUXA/Band main are in power good mode. AUX PG(A/B) (R) : This bit indicates the power good status on the VAUXA/B outputs. • 1 – VAUXA/B output is above the power good threshold.
TPS2363 www.ti.com SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 Table 9. STAT A (04h), STAT B (05h): Default 00h FAULTA/B MAINA/B AUXA/B VAUXFA/B RSVD 12VFA/B RSVD 3VFA/B R R R R/W R R/W R R/W Valid write commands: The write commands are used to clear the faults in these registers. • 00h, 01h, 04h, 05h, 10h, 11h, 14h, 15h Valid read commands: 0Y through fY (Y corresponds to 0, 1, 4, or 5) FAULT A/B : This bit indicates the status of the FAULTA/B pin. • 1 – FAULTA/B pin is low.
TPS2363 SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 www.ti.com When TPS2363 is enabled using SMBus for control, this bit needs to be cleared by the master – ECHO RESET condition. i.e., a “1” is written into this bit by the master. Once this is done, pin INT will be de-asserted i.e., it goes high. 3VFA/B : This bit indicates an over current fault condition on 3.3 V out – A • 1 – There is an over current condition on 3.3 V out A i.e.
TPS2363 www.ti.com SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 UV_INT: This bit indicates the UVLO condition on the main supplies only. The status of this bit depends on the conditions on main enable pins or the main enable bits in the control register. If the main supplies are disabled, this bit is 0. • 1 – UVLO fault. (and supplies are enabled) • 0 – No UVLO fault. Supplies are above UVLO thresholds. When using SMBUS, this bit is reset using the ECHO reset condition.
TPS2363 SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 www.ti.com Typical Characteristics Figure 15. Over Current Applied to 3.3 V - FAULT & PGOOD Figure 16. Over Current Applied to 3.
TPS2363 www.ti.com SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 Typical Characteristics (continued) Figure 17. Short applied to 3.3V Figure 18.
TPS2363 SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 www.ti.com Typical Characteristics (continued) Figure 19. Turn Off of the Main Voltages Figure 20.
TPS2363 www.ti.com SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 Typical Characteristics (continued) Figure 21. Short Applied to AUX Figure 22.
TPS2363 SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 www.ti.com Typical Characteristics (continued) Figure 23. AUX Disable Turn Off Figure 24.
TPS2363 www.ti.com SLUS680B – JANUARY 2006 – REVISED JANUARY 2010 Typical Characteristics (continued) Figure 25. Over Current Applied to 12V Figure 26.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS2363PFBR Package Package Pins Type Drawing TQFP PFB 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 9.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.6 1.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2363PFBR TQFP PFB 48 1000 367.0 367.0 38.
MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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