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OUT

VC1

GATE

ARTN

CTL

DEN

From Ethernet

Pairs 1,2

CTL

From Ethernet

Pairs 3,4

CLS

DEN

FRS

T2P

CLS

T2P-OUT

Type2PSE

Indicator

FRS

FBU

FBL

TLV431

OUT

PAD

DD1

GAT2

T2P

APD2

APD1

N/CORPPD

Adapter

BLNK

APD

BLNK

RTN

COM

OUT

VC2

Optional

Interface

T2P-OUT

TPS23754

TPS23754-1

TPS23756

www.ti.com

SLVS885G –OCTOBER 2008–REVISED OCTOBER 2013

High Power/High Efficiency PoE Interface and DC/DC Controller

FEATURES

The TPS23754 and TPS23756 support a number of

• Powers up to 30-W (Input) PDs

input voltage ORing options including highest voltage,

• DC/DC Control Optimized for Isolated

external adapter preference, and PoE preference.

Converters

These features allow the designer to determine which

• Supports High-Efficiency Topologies

power source will carry the load under all conditions.

• Complete PoE Interface

The PoE interface features the new extended

• Enhanced Classification per IEEE 802.3at With

hardware classification necessary for compatibility

Status Flag

with high-power midspan power sourcing equipment

(PSE) per IEEE 802.3at. The detection signature pin

• Adapter ORing Support

can also be used to force power from the PoE source

• Programmable Frequency With

off. Classification can be programmed to any of the

Synchronization

defined types with a single resistor.

• Robust 100-V, 0.5-Ω Hotswap MOSFET

The DC/DC controller features two complementary

• –40°C to 125°C Junction Temperature Range

gate drivers with programmable dead time. This

simplifies the design of active-clamp forward

• Industry Standard PowerPAD™ TSSOP-20

converters or optimized gate drive for highly-efficient

flyback topologies. The second gate driver may be

APPLICATIONS

disabled if desired for single MOSFET topologies.

• IEEE 802.3at Compliant Devices

The controller also features internal softstart,

bootstrap startup source, current-mode

• Video and VoIP Telephones

compensation, and a 78% maximum duty cycle. A

• RFID Readers

programmable and synchronizable oscillator allows

• Multiband Access Points

design optimization for efficiency and eases use of

• Security Cameras

the controller to upgrade existing power supply

designs. Accurate programmable blanking, with a

default period, simplifies the usual current-sense filter

DESCRIPTION

design trade-offs.

The TPS23754 and TPS23756 devices have a

combined power-over-ethernet (PoE) powered-device

The TPS23754 device has a 15-V converter startup

(PD) interface and current-mode DC/DC controller

while the TPS23756 device has a 9-V converter

optimized specifically for isolated converters. The

startup. The TPS23754-1 replaces the PPD pin with a

PoE interface supports the IEEE 802.3at standard.

no-connect for increased pin spacing.

Figure 1. High Efficiency Converter Using TPS23754

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD, TSSOP-20 PowerPAD, PowerPad are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (45 pages)

PAGE 1
TPS23754 TPS23754-1 TPS23756 www.ti.com SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 High Power/High Efficiency PoE Interface and DC/DC Controller FEATURES 1 • • • • • The PoE interface features the new extended hardware classification necessary for compatibility with high-power midspan power sourcing equipment (PSE) per IEEE 802.3at. The detection signature pin can also be used to force power from the PoE source off.
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TPS23754 TPS23754-1 TPS23756 SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS23754 TPS23754-1 TPS23756 www.ti.
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TPS23754 TPS23754-1 TPS23756 SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 www.ti.com PARAMETER TEST CONDITIONS MIN TYP MAX 227 253 UNIT FRS Switching frequency CTL = VB, measure GATE RFRS = 68.1 kΩ DMAX Duty cycle CTL= VB, measure GATE VSYNC Synchronization Input threshold 0% duty cycle threshold Softstart period 278 kHz 76 78 80 % 2 2.2 2.4 V VCTL ↓ until GATE stops 1.3 1.5 1.7 V Interval from switching start to VCSMAX 1.9 3.9 6.
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TPS23754 TPS23754-1 TPS23756 www.ti.com SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 ELECTRICAL CHARACTERISTICS – PoE AND CONTROL [VDD = VDD1] or [VDD1 = RTN], VC = RTN, COM = RTN = ARTN, all voltages referred to VSS unless otherwise noted PARAMETER DETECTION (DEN) TEST CONDITIONS MIN TYP MAX UNIT (VDD = VDD1 = RTN = VSUPPLY positive) Measure ISUPPLY Detection current Detection bias current VPD_DIS VDD = 1.6 V 62 64.3 66.5 VDD = 10 V 399 406 414 5.6 10 μA 4 5 V 0.1 5 μA 1.8 2.
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TPS23754 TPS23754-1 TPS23756 GATE SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 www.ti.com hi 50% GAT2 lo hi 50% time lo tDT1 tDT2 Figure 2. GATE and GAT2 Timing and Phasing DEVICE INFORMATION FUNCTIONAL BLOCK DIAGRAM VC VDD1 f f Oscillator FRS CTL 50kW 4ms Softstart Control Global Cvtr. Enable enb enb + D Q CK 1 + 0.75V CLRB ARTN 40mA (pk) ss CTL - 0.55V T2P Logic t2 Converter Thermal Monitor + T2P ARTN BLNK ARTN VDD DT COM GAT2 Switch Matrix ARTN GATE f 3.
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TPS23754 TPS23754-1 TPS23756 www.ti.com SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 (TOP VIEW) TPS23754/6 CTL VB CS COM GATE VC GAT2 ARTN RTN VSS 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 TPS23754-1 T2P FRS BLNK APD DT CLS PPD DEN VDD VDD1 CTL VB CS COM GATE VC GAT2 ARTN RTN VSS 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 PAD = V SS T2P FRS BLNK APD DT CLS N/C DEN VDD VDD1 PAD = V SS N/C = Leave Pin Unused PIN FUNCTIONS NO.
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TPS23754 TPS23754-1 TPS23756 SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 www.ti.com PIN FUNCTIONS (continued) NO. NAME TPS23754 TPS2375 and 4-1 TPS23756 VDD1 11 11 VSS 10 10 TYPE I DESCRIPTION Source of DC/DC converter startup current. Connect to VDD for many applications. Connect to the negative power rail derived from the PoE source.
PAGE 9
TPS23754 TPS23754-1 TPS23756 www.ti.com SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 Table 1. Class Resistor Selection POWER AT PD RESISTOR (Ω) CLASS MINIMUM (W) MAXIMUM (W) 0 0.44 13.0 1270 1 0.44 3.84 243 2 3.84 6.49 137 3 6.49 13.0 90.9 4 13.0 25.5 63.4 NOTES Minimum may be reduced by pulsed loading. Serves as a catch-all default class. Not allowed prior to IEEE 802.3at. Use to indicate a Type 2 PD (high power) device per IEEE 802.3at.
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TPS23754 TPS23754-1 TPS23756 SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 www.ti.com The converter may be synchronized to a frequency above its maximum free-running frequency by applying short AC-coupled pulses into the FRS pin per Figure 30. The FRS pin is high impedance. Keep the connections short and apart from potential noise sources. Special care should be taken to avoid crosstalk when synchronizing circuits are used. GATE Gate drive output for the DC/DC converter’s main switching MOSFET.
PAGE 11
TPS23754 TPS23754-1 TPS23756 www.ti.com SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 VB VB is an internal 5.1-V regulated DC/DC controller supply rail that is typically bypassed by a 0.1-μF capacitor to ARTN. VB should be used to bias the feedback optocoupler. VC VC is the bias supply for the DC/DC controller. The MOSFET gate drivers run directly from VC. VB is regulated down from VC, and is the bias voltage for the rest of the converter control.
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TPS23754 TPS23754-1 TPS23756 SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 www.ti.com TYPICAL CHARACTERISTICS DETECTION BIAS CURRENT vs VOLTAGE PoE CURRENT LIMIT vs TEMPERATURE 970 8 Pulsed Current Measurement 7 960 PoE − Current Limit − mA IVDD − Bias Current − µA 6 25°C 5 125°C 4 3 2 950 940 930 −40°C 920 1 0 0 2 4 6 8 910 −40 10 (VVDD − VVSS) − PoE Voltage − V −20 0 20 40 80 100 G001 Figure 3. Figure 4.
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TPS23754 TPS23754-1 TPS23756 www.ti.com SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 TYPICAL CHARACTERISTICS (continued) '754 CONVERTER STARTUP CURRENT vs VVDD1 6 '756 CONVERTER STARTUP CURRENT vs VVDD1 6 VVC = 13.9V VVC = 8.6V o TJ = -40oC TJ = -40 C 5 IVC − Source Current − mA IVC − Source Current − mA 5 o TJ = 25 C 4 o TJ = 125 C 3 2 1 o TJ = 25 C 4 TJ = 125oC 3 2 1 0 0 5 10 15 20 25 30 35 40 45 50 55 60 5 10 15 20 VVDD1-RTN − V 35 40 45 50 Figure 7.
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TPS23754 TPS23754-1 TPS23756 SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) '756 CONTROLLER BIAS CURRENT vs VOLTAGE SWITCHING FREQUENCY vs TEMPERATURE 1200 600 4000 GATE, GAT2 open o TJ = 25 C 3500 RFRS = 34.6 kΩ (484 kHz) 1100 500 VC − Bias Current − mA 3000 2500 480 kHz 2000 100 kHz 1500 50 kHz 400 300 1000 RFRS = 17.35 kΩ (937 kHz) 900 RFRS = 69.
PAGE 15
TPS23754 TPS23754-1 TPS23756 www.ti.com SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 TYPICAL CHARACTERISTICS (continued) CURRENT SLOPE COMPENSATION VOLTAGE vs TEMPERATURE CURRENT SLOPE COMPENSATION CURRENT vs TEMPERATURE 50 155 154 45 ISLOPE − µAPP VSLOPE − mVPP 153 152 40 151 35 150 20 40 60 80 100 Blanking Period − ns 60 80 BLANKING PERIOD vs TEMPERATURE BLANKING PERIOD vs Blanking Resistance (RBLNK) 260 255 RBLNK = 100 kΩ 250 85 RBLNK = 249 kΩ 245 75 450 RBLNK = 49.
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TPS23754 TPS23754-1 TPS23756 SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) DEAD TIME vs DEAD TIME RESISTANCE (RDT ) T2P DELAY TIME vs TEMPERATURE 11 900 800 10 Ideal T2P Delay Time - ms Dead Time - ns 700 600 500 400 Typical 300 200 9 8 7 100 0 0 50 100 150 200 250 300 Dead Time Resistance - kW Figure 19. 16 Submit Documentation Feedback 350 400 6 -40 -20 0 20 40 60 80 Temperature - °C 100 120 Figure 20.
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TPS23754 TPS23754-1 TPS23756 www.ti.com SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 DETAILED DESCRIPTION PoE OVERVIEW The following text is intended as an aid in understanding the operation of the TPS23754, but not as a substitute for the IEEE 802.3at standard. The IEEE 802.3at standard is an update to IEEE 802.3-2008 clause 33 (PoE), adding high-power options and enhanced classification. Generally speaking, a device compliant to IEEE 802.
PAGE 18
TPS23754 TPS23754-1 TPS23756 SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 www.ti.com Table 2. Comparison of Operational Limits STANDARD POWER LOOP RESISTANCE (max) PSE OUTPUT POWER (min) PSE STATIC OUTPUT VOLTAGE (min) PD INPUT POWER (max) POWER ≤ 13.0 W STATIC PD INPUT VOLTAGE POWER > 13.0 W IEEE 802.3-2008 802.3at (Type 1) 20 Ω 15.4 W 44 V 13.0 W 37 – 57 V N/A 802.3at (Type 2) 12.5 Ω 30 W 50 V 25.5 W 37 – 57 V 42.
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TPS23754 TPS23754-1 TPS23756 www.ti.com SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 PoE Startup Sequence 50 mA/div The waveforms of Figure 23 demonstrate detection, classification, and startup from a PSE with type 2 hardware classification. The key waveforms shown are VVDD-VVSS, VRTN-VVSS, and IPI. IEEE 802.3at requires a minimum of two detection levels, two class and mark cycles, and startup from the second mark event.
PAGE 20
TPS23754 TPS23754-1 TPS23756 SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 www.ti.com The maximum power entries in Table 1 determine the class the PD must advertise. The PSE may disconnect a PD if it draws more than its stated class power, which may be the hardware class or a lower DLL-derived power level. The standard permits the PD to draw limited current peaks that increase the instantaneous power above the Table 1 limit; however, the average power requirement always applies.
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TPS23754 TPS23754-1 TPS23756 www.ti.com SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 Maintain Power Signature The MPS is an electrical signature presented by the PD to assure the PSE that it is still present after operating voltage is applied. A valid MPS consists of a minimum DC current of 10 mA (or a 10-mA pulsed current for at least 75 ms every 325 ms) and an AC impedance lower than 26.3 kΩ in parallel with 0.05 μF.
PAGE 22
TPS23754 TPS23754-1 TPS23756 SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 www.ti.com PD Hotswap Operation IEEE 802.3at has taken a new approach to PSE output limiting. A type 2 PSE must meet an output current versus time template with specified minimum and maximum sourcing boundaries. The peak output current may be as high as 50 A for 10 μs or 1.75 A for 75 ms. This makes robust protection of the PD device even more important than it was in IEEE 802.3-2008.
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TPS23754 TPS23754-1 TPS23756 www.ti.com SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 The TPS23754 is optimized for isolated converters, and does not provide an internal error amplifier. Instead, the optocoupler feedback is directly fed to the CTL pin which serves as a current-demand control for the PWM. There is an offset of VZDC (about 1.5 V) and 2:1 resistor divider between the CTL pin and the PWM.
PAGE 24
TPS23754 TPS23754-1 TPS23756 SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 www.ti.com The TPS23754 device blanker timing is precise enough that the traditional R-C filters on CS can be eliminated. This avoids current-sense waveform distortion, which tends to get worse at light output loads. There may be some situations or designers that prefer an R-C approach. The TPS23754 device provides a pull-down on CS during the GATE off time to improve sensing when an R-C filter must be used.
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TPS23754 TPS23754-1 TPS23756 www.ti.com SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 Adapter ORing Many PoE-capable devices are designed to operate from either a wall adapter or PoE power. A local power solution adds cost and complexity, but allows a product to be used if PoE is not available in a particular installation. While most applications only require that the PD operate when both sources are present, the TPS23754 device supports forced operation from either of the power sources.
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TPS23754 TPS23754-1 TPS23756 SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 www.ti.com ORing Challenges Preference of one power source presents a number of challenges. Combinations of adapter output voltage (nominal and tolerance), power insertion point, and which source is preferred determine solution complexity.
PAGE 27
TPS23754 TPS23754-1 TPS23756 www.ti.com SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 Input Bridges and Schottky Diodes Using Schottky diodes instead of PN junction diodes for the PoE input bridges and DVDD will reduce the loss of this function by about 30%. However, there are some things to consider when using them. The IEEE standard specifies a maximum backfeed voltage of 2.8 V. A 100-kΩ resistor is placed between the unpowered pairs and the voltage is measured across the resistor.
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TPS23754 TPS23754-1 TPS23756 SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 www.ti.com Classification Resistor, RCLS Connect a resistor from CLS to VSS to program the classification current according to the IEEE 802.3at standard. The class power assigned should correspond to the maximum average power drawn by the PD during operation. Select RCLS according to Table 1. For a high-power design, choose class 4 and RCLS = 63.4 Ω.
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TPS23754 TPS23754-1 TPS23756 www.ti.com SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 2. Compute RFRS: RFRS (k W ) = 17250 17250 = = 69 fSW (kHz) 250 (a) (b) Select 69.8 kΩ. VSYNC FRS 47pF VSYNC TSYNC 1000pF RFRS TSYNC RFRS 47pF Synchronization Pulse RT FRS RTN ARTN COM Synchronization Pulse RTN ARTN COM The TPS23754 device may be synchronized to an external clock to eliminate beat frequencies from a sampled system, or to place emission spectrum away from an RF input frequency.
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TPS23754 TPS23754-1 TPS23756 SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 www.ti.com Blanking Period, RBLNK Selection of the blanking period is often empirical because it is affected by parasitics and thermal effects of every device between the gate-driver and output capacitors. The minimum blanking period prevents the current limit and PWM comparators from being falsely triggered by the inherent current spike that occurs when the switching MOSFET turns on.
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TPS23754 TPS23754-1 TPS23756 www.ti.com SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 3. Compute the required CVC based on startup within the typical softstart period of 4 ms. CVC1 + CVC2 = TSTARTUP ´ ITOTAL 4 ms ´ 8.42 mA = = 5.18 mF VCUVH 6.5 V (a) (b) For this case, a standard 10-μF electrolytic plus a 0.47 μF should be sufficient. 4. Compute the initial time to start the converter when operating from PoE. (a) Using a typical bootstrap current of 4 mA, compute the time to startup. C ´ VCUV 10.
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TPS23754 TPS23754-1 TPS23756 SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 www.ti.com VC RT2P VOUT RT2P_OUT Type 2 PSE Indicator Low = T2 T2P From TPS23754 Figure 33. T2P Interface 1. T2P ON characteristic: IT2P = 2 mA minimum, VT2P = 1 V 2. Let VC = 12 V, VOUT = 5 V, RT2P-OUT = 10 kΩ, VT2P-OUT (low) = 400 mV max V - VT2P-OUT (low) 5 - 0.4 IRT2P-OUT = OUT = = 0.46 m A R T2P-OUT 10000 (a) 3. The optocoupler CTR will be needed to determine RT2P.
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TPS23754 TPS23754-1 TPS23756 SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 CVDD 10nF VDD VDD1 DA 30V 26.7kW APD 3.01kW VSS RAPD2 RAPD1 DAPD CIN RTN COM ARTN RDEN 3.3MW RVDD1 RAPD2 DRTN RTN COM ARTN APD RAPD1 PPD DEN CLS RCLS VSS 58V CIN 1.8KW RHLD For 48V Adapter 24V VDD1 PPD DEN CLS DA Adapter DVDD DHLD RCLS VDD RDEN 1.8kW 24V D1 58V DVDD C1 0.1uF From Spare Pairs or Transformers From Ethernet Transformers www.ti.com Adapter Figure 34.
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TPS23754 TPS23754-1 TPS23756 SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 www.ti.com From Regulated Output Voltage ROB RSS RFBU CIZ DSS CSS RFBL TLV431 Figure 36. Error Amplifier Softstart Special Switching MOSFET Considerations Special care must be used in selecting the converter switching MOSFET. The TPS23756 minimum switching MOSFET VGATE is about 5.5 V, which is due to the VC lower threshold. This will occur during an output overload, or toward the end of a (failed) bootstrap startup.
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TPS23754 TPS23754-1 TPS23756 www.ti.com SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 ESD The TPS23754 device has been tested to EN61000-4-2 using a power supply based on Figure 1. The levels used were 8-kV contact discharge and 15-kV air discharge. Surges were applied between the PoE input and the DC output, between the adapter input and the DC output, between the adapter and the PoE inputs, and to the DC output with respect to earth. Tests were done both powered and unpowered.
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TPS23754 TPS23754-1 TPS23756 SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 www.ti.com REVISION HISTORY Changes from Revision A (April 2009) to Revision B Page • Deleted The TPS23756 is at PREVIEW status. ................................................................................................................... 1 • Changed Preview ..................................................................................................................................................................
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TPS23754 TPS23754-1 TPS23756 www.ti.com SLVS885G – OCTOBER 2008 – REVISED OCTOBER 2013 • Updated equations for RPPD1, VADPTR_ON, and VADPTR_OFF to have one subtraction instead be an addition and changed the end value obtained. ........................................................................................................................................ 28 • Added more information regarding use of the PPD pin to modify the internal MOSFET UVLO. .......................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 7-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 7-Nov-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TPS23754PWPR HTSSOP PWP 20 2000 330.0 16.4 TPS23754PWPR-1 HTSSOP PWP 20 2000 330.0 TPS23756PWPR HTSSOP PWP 20 2000 330.0 6.95 7.1 1.6 8.0 16.0 Q1 16.4 6.95 7.1 1.6 8.0 16.0 Q1 16.4 6.95 7.1 1.6 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 7-Nov-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS23754PWPR HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS23754PWPR-1 HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS23756PWPR HTSSOP PWP 20 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.