Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - PoE controller TSSOP 20 Controller (PD) DC/DC

Optional

Interface

OUT2

VC1

GATE

RTN, COM

ARTN

CTL

58V

0.1 Fm

DEN

FromEthernet

Pairs1,2

CTL

FromEthernet

Pairs3,4

CLS

DEN

FRS

APb

CLS

APb_OUT

Adapter

Presentand

Converter

Running

FRS

FBU

FBL

TLV431

OUT

GAT2

APb

APD2

APD1

PPD

Adapter

BLNK

APD

BLNK

DD1

OUT1

OUT

APb_OUT

TPS23757

www.ti.com

SLVS948D –JULY 2009–REVISED NOVEMBER 2013

High Efficiency PoE Interface and DC/DC Controller

The TPS23757 supports a number of input voltage

FEATURES

ORing options including highest voltage, external

• Powers up to 13 W (Input) PDs

adapter preference, and PoE preference.

• Legacy and IEEE 802.3at Type 1 PDs

The TPS23757 has an output flag indicating if an

• Optimized for Isolated DC/DC Converters

external wall adapter is active when used in

• Supports High-Efficiency Topologies

conjunction with ORing controls. The detection

signature pin can also be used to force power from

• Complete PoE Interface

the PoE source off. Classification can be

• Adapter ORing Support

programmed to any of the defined types with a single

• Programmable Frequency with Synch.

resistor.

• Robust 100 V, 0.5 Ω Hotswap MOSFET

The dc/dc controller features two complementary gate

• Pin Compatible with TPS23754/6

drivers with programmable dead time. This simplifies

design of highly-efficient flyback topologies or active-

• –40°C to 125°C Junction Temperature Range

clamp forward or flyback converters. The second gate

• Industry Standard TSSOP-20

driver may be disabled if desired for single MOSFET

topologies. The controller also features internal

APPLICATIONS

softstart, bootstrap startup source, current-mode

compensation, and a 78% maximum duty cycle. A

• IEEE 802.3at Type 1 Compliant Devices

programmable and synchronizable oscillator allows

• Video and VoIP Telephones

design optimization for efficiency and eases use of

• Access Points

the controller to upgrade existing power supply

designs. Accurate programmable blanking, with a

• Security Cameras

default period, simplifies the usual current- sense

filter design trade-offs.

DESCRIPTION

The TPS23757 is a combined Power over Ethernet The TPS23757 has a 9 V converter startup,

(PoE) powered device (PD) interface and current- permitting operation with 12 V wall adapters.

mode dc/dc controller optimized specifically for

isolated converters. The PoE interface supports the

IEEE 802.3at standard for a type 1 PD, which is

equivalent to the 13W standard of IEEE 802.3-2008.

Figure 1. High Efficiency Converter Using TPS23757

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (39 pages)

PAGE 1
TPS23757 www.ti.com SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 High Efficiency PoE Interface and DC/DC Controller FEATURES The TPS23757 supports a number of input voltage ORing options including highest voltage, external adapter preference, and PoE preference. 1 Powers up to 13 W (Input) PDs Legacy and IEEE 802.3at Type 1 PDs Optimized for Isolated DC/DC Converters Supports High-Efficiency Topologies Complete PoE Interface Adapter ORing Support Programmable Frequency with Synch. Robust 100 V, 0.
PAGE 2
TPS23757 SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
TPS23757 www.ti.com SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 RECOMMENDED OPERATING CONDITIONS (1) Voltage with respect to VSS (unless otherwise noted) MIN VI UNIT 0 57 V Input voltage range APb, VC to [ARTN, COM] 0 18 V Input voltage range APD, CTL to [ARTN, COM] 0 VB V Input voltage range CS to [ARTN, COM] 0 2 V Continuous RTN current (TJ ≤ 125°C) IS Sourcing current, VB C VB capacitance (2) 0 400 mA 5 mA 2.5 μF 0.
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TPS23757 SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 www.ti.com PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 227 253 278 kHz 76 78 80 % 2 2.2 2.4 V FRS Switching frequency CTL = VB, measure GATE, RFRS = 68.1 kΩ DMAX Duty cycle CTL= VB, measure GATE VSYNC Synchronization Input threshold 0% duty cycle threshold VCTL ↓ until GATE stops 1.3 1.5 1.7 V Softstart period Interval from switching start to VCSMAX 1.9 3.9 6.2 ms 70 100 145 kΩ BLNK = RTN 35 55 78 RBLNK = 49.
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TPS23757 www.ti.com SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 ELECTRICAL CHARACTERISTICS – PoE AND CONTROL [VDD = VDD1] or [VDD1 = RTN], VC = RTN, COM = RTN = ARTN, all voltages referred to VSS unless otherwise noted PARAMETER TEST CONDITIONS DETECTION (DEN) MIN TYP MAX UNIT (VDD = VDD1 = RTN = VSUPPLY positive) Measure ISUPPLY Detection current VDD = 1.6 V 62 64.3 66.5 VDD = 10 V 399 406 414 5.6 10 4 5 V 0.1 5 μA 1.8 2.1 2.4 RCLS = 243 Ω 9.9 10.4 10.9 RCLS = 137 Ω 17.
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TPS23757 SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 www.ti.com DEVICE INFORMATION FUNCTIONAL BLOCK DIAGRAM VDD1 VC f Oscillator FRS CTL 50kW CONV. OFF enb 4 ms Softstart Control D Q CK 1 + CLRB 40mA (pk) DT COM GAT 2 Converter Thermal Monitor + 0.55V - ARTN sa pa softstart CTL APb Logic Switch Matrix ARTN BLNK ARTN VDD GATE f 375kW CS VB Ref Global Cvtr. enb Enable + 0.75V ARTN Reg Deadtime 50kW f 2.
PAGE 7
TPS23757 www.ti.com SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 PIN FUNCTIONS NAME NO. TYPE DESCRIPTION CTL 1 I The control loop input to the PWM (pulse width modulator), typically driven by output regulation feedback (e.g. optocoupler). Use VB as a pullup for CTL. VB 2 O 5.1 V bias rail for dc/dc control circuits and the feedback optocoupler. Typically bypass with a 0.1 μF to ARTN. CS 3 I/O DC/DC converter switching MOSFET current sense input. See RCS in Figure 1.
PAGE 8
TPS23757 SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 www.ti.com BLNK Blanking provides an interval between GATE going high and the current-control comparators on CS actively monitoring the input. This delay allows the normal turn-on current transient (spike) to subside before the comparators are active, preventing undesired short duty cycles and premature current limiting. Connect BLNK to ARTN to obtain the internally set blanking period.
PAGE 9
TPS23757 www.ti.com SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 DT Dead-time programming sets the delay between GATE and GAT2 to prevent overlap of MOSFET ON times as shown in Figure 2. GAT2 turns the second MOSFET OFF when it transitions high. Both MOSFETs should be OFF between GAT2 going high to GATE going high, and GATE going low to GAT2 going low. The maximum GATE ON time is reduced by the programmed dead-time period. The dead time period is specified with 1 nF of capacitance on GATE and GAT2.
PAGE 10
TPS23757 SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 www.ti.com The PPD pin has a 5 μA internal pull-down current. Locate the PPD pull-down resistor adjacent to the pin when used. PPD may be tied to VSS or left open when not used. RTN, ARTN, COM RTN is internally connected to the drain of the PoE hotswap MOSFET, while ARTN is the quiet analog return for the dc/dc controller. COM serves as the return path for the gate drivers and should be tied to ARTN on the circuit board.
PAGE 11
TPS23757 www.ti.com SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 TYPICAL CHARACTERISTICS DETECTION BIAS CURRENT vs VOLTAGE PoE CURRENT LIMIT vs TEMPERATURE 8 485 7 480 25°C Current Limit − mA IVDD − Bias Current − µA 6 5 125°C 4 3 475 470 2 −40°C 465 1 0 0 2 4 6 8 460 −40 10 0 20 40 60 80 100 120 TJ - Junction Temperature - C G001 Figure 3. Figure 4. CONVERTER START TIME vs TEMPERATURE CONVERTER STARTUP CURRENT vs VVDD1 160 6 VVC = 8.6V VVDD1 = 10.
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TPS23757 SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 www.ti.
PAGE 13
TPS23757 www.ti.com SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 TYPICAL CHARACTERISTICS (continued) MAXIMUM DUTY CYCLE vs TEMPERATURE CURRENT SLOPE COMPENSATION VOLTAGE vs TEMPERATURE 79 155 78 RFRS = 347 kW (50 kHz) 154 RFRS = 69.8 kW (245 kHz) 76 153 VSLOPE − mVPP Maximum Duty Cycle − % 77 75 RFRS = 34.6 kW (484 kHz) 74 RFRS = 26.7 kW (623 kHz) 73 152 151 RFRS = 21.
PAGE 14
TPS23757 SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 www.ti.
PAGE 15
TPS23757 www.ti.com SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 DETAILED DESCRIPTION PoE OVERVIEW The following text is intended as an aid in understanding the operation of the TPS23757 but not as a substitute for the IEEE 802.3at standard. The IEEE 802.3at standard is an update to IEEE 802.3-2008 clause 33 (PoE), adding high-power options and enhanced classification. Generally speaking, a device compliant to IEEE 802.
PAGE 16
TPS23757 SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 www.ti.com The PD input, typically an RJ-45 eight-lead connector, is referred to as the power interface (PI). PD input requirements differ from PSE output requirements to account for voltage drops in the channel and operating margin. The standard allots the maximum loss to the cable regardless of the actual installation to simplify implementation. IEEE 802.3-2008 (and IEEE 802.
PAGE 17
TPS23757 www.ti.com SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 Cvtr. Starts Inrush 50 mA/div IPI Class 10 V/div Detect (Four Point) VVDD - VVSS VRTN - VVSS t - Time - 50 ms/div Figure 20. Startup Detection The TPS23757 drives DEN to VSS whenever VVDD-VVSS is in the detection state per Figure 19. When the input voltage rises above VCL-ON, the DEN pin goes to an open-drain condition to conserve power. While in detection, RTN is high impedance, and almost all the internal circuits are disabled.
PAGE 18
TPS23757 SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 www.ti.com Inrush and Startup The TPS23757 provides a 140 mA inrush limit that is compatible with both type 1 and type 2 PSEs. The TPS23757’s internal softstart permits control of the converter startup preventing the converter from exceeding the PSE output limitations. APb becomes valid within tAPb after converter switching starts, or if an adapter is plugged in while the PD is operating from a PSE.
PAGE 19
TPS23757 www.ti.com SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 If VVDD- VVSS drops below the lower PoE UVLO (VUVLO-R – VUVLO-H, ~30.5 V), the hotswap MOSFET is turned off, but the converter will still run. The converter will stop if VVC falls below the converter UVLO (VCUV – VCUVH, ~5.5 V), the hotswap is in inrush current limit, 0% duty cycle is demanded by VCTL (VCTL < VZDC, ~1.5 V), or the converter is in thermal shutdown. PD Hotswap Operation IEEE 802.
PAGE 20
TPS23757 SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 www.ti.com Converter Controller Features The TPS23757 dc/dc controller implements a typical current-mode control as shown in the Functional Block Diagram. Features include oscillator, overcurrent and PWM comparators, current-sense blanker, dead-time control, softstart, and gate driver. In addition, an internal slope-compensation ramp generator, frequency synchronization logic, thermal shutdown, and startup current source with control are provided.
PAGE 21
TPS23757 www.ti.com SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 Blanking - RBLNK The TPS23757 provides a choice between internal fixed and programmable blanking periods. The blanking period is specified as an increase in the minimum GATE on time over the inherent gate driver and comparator delays. The default period (see the Electrical Characteristics table) is selected by connecting BLNK to RTN, and the programmable period is set with RBLNK.
PAGE 22
TPS23757 SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 www.ti.com Adapter ORing Many PoE-capable devices are designed to operate from either a wall adapter or PoE power. A local power solution adds cost and complexity, but allows a product to be used if PoE is not available in a particular installation. While most applications only require that the PD operate when both sources are present, the TPS23757 supports forced operation from either of the power sources.
PAGE 23
TPS23757 www.ti.com SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 Several examples will demonstrate the limitations inherent in ORing solutions. Diode ORing a 48 V adapter with PoE (option 1) presents the problem that either source might be higher. A blocking switch would be required to assure which source was active. A second example is combining a 12 V adapter with PoE using option 2. The converter will draw approximately four times the current at 12 V from the adapter than it does from PoE at 48 V.
PAGE 24
TPS23757 SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 www.ti.com Use of diode DVDD for PoE priority may dictate the use of additional protection around the TPS23757. ESD events between the PD power inputs (PoE and adapter), or the inputs and converter output, cause large stresses in the hotswap MOSFET if DVDD becomes reverse biased and transient current around the TPS23757 is blocked. The use of CVDD and DRTN in Figure 24 provides additional protection should over-stress of the TPS23757 be an issue.
PAGE 25
TPS23757 www.ti.com SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 æ ö æ ö çV - VPPDEN ÷ ç 18 V - 1.55 V ÷ ADPTR_ON ÷ =ç RPPD1 = ç ÷ = 31.64 kW VPPDEN ç ÷ ç 1.55 V ÷÷ + m 5 A + I ç PPD ç ÷ è 3.01 kW R ø PPD2 è ø (a) (b) Choose RPPD1 = 32.4 kΩ 5. Check PPD turn on and PPD turn off voltages é æV öù VADPTR_ON = VPPDEN + êRPPD1 ´ ç PPDEN + IPPD ÷ ú = 18.4 V è RPPD2 ø ûú ëê (a) é æ (VPPDEN - VPPDH ) öù + IPPD ÷ ú = 14.
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TPS23757 VSYNC FRS 47pF VSYNC TSYNC 1000pF RFRS TSYNC RFRS 47pF Synchronization Pulse RT FRS RTN ARTN COM Synchronization Pulse www.ti.com RTN ARTN COM SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 1:1 Figure 25. Synchronization Current Slope Compensation The TPS23757 provides a fixed internal compensation ramp that suffices for most applications. RS (see Figure 26) may be used if the internally provided slope compensation is not enough.
PAGE 27
TPS23757 www.ti.com RBLNK (k W ) = SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 BIanking_Interval(%) 2 ´ 10 4 = ´ 10 4 = 80 fSW (kHz) 250 (a) (b) Select RBLNK = 80.6 kΩ. Dead Time Resistor, RDT The required dead time period depends on the specific topology and parasitics. To obtain the optimum timing resistor, build the supply and tune the dead time to achieve the best efficiency after considering all corners of operation (load, input voltage, and temperature). A good initial value is 100 ns.
PAGE 28
TPS23757 SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 www.ti.com (CVC1 + CVC2 ) ´ VCUVH (10 mF + 0.47 mF) ´ 3.5 V = = 9.2 ms IVC 4 mA (CVC1 + CVC2 ) ´ VCUVH (10 mF + 0.47 mF) ´ 3.5 V tDISCHARGE = = = 6.5 ms ITOTAL 5.6 mA (a) Note that the optocoupler current is 0 mA because the output is in current limit. (b) Also, it is assumed IAPb is 0 mA. tDISCHARGE 6.5 ms Duty Cycle: D = = = 41% tDISCHARGE + tRECHARGE 6.5 ms + 9.2 ms 1 1 Hiccup Frequency: F = = = 64 Hz tDISCHARGE + tRECHARGE 6.5 ms + 9.
PAGE 29
TPS23757 www.ti.com SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 IAPb = VOUT - VAPb (low) 5 - 0.4 = = 0.46 mA R APb 10000 (a) 3. The optocoupler CTR will be needed to determine RAPb. A device with a minimum CTR of 300% at 5 mA LED bias current is selected. CTR will also vary with temperature and LED bias current. The strong variation of CTR with diode current makes this a problem that requires some iteration using the CTR versus IDIODE curve on the optocoupler data sheet.
PAGE 30
TPS23757 SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 www.ti.com VDD VDD1 DEN PPD CLS RCLS D1 58V From Spare Pairs or Transformers C1 0.1uF RDEN From Ethernet Transformers Option 1 ORing of a low voltage adapter (e.g., 24 V) is possible by connecting a resistor divider to PPD as in Figure 30. When 1.55 V ≤ VPPD ≤ 8.3 V, the hotswap MOSFET is enabled, APb is activated, and the class feature is disabled. The hotswap current limit is unaffected, limiting the available power.
PAGE 31
TPS23757 www.ti.com SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 Special Switching MOSFET Considerations Special care must be used in selecting the converter switching MOSFET. The TPS23757 minimum switching MOSFET VGATE is ~5.5 V, which is due to the VC lower threshold. This will occur during an output overload, or towards the end of a (failed) bootstrap startup. The MOSFET must be able to carry the anticipated peak fault current at this gate voltage.
PAGE 32
TPS23757 SLVS948D – JULY 2009 – REVISED NOVEMBER 2013 www.ti.com REVISION HISTORY Changes from Revision Original (August 2009) to Revision A • Page Changed the ESDS statement. ............................................................................................................................................. 2 Changes from Revision A (September 2009) to Revision B Page • Changed From: IEEE 802.3at (draft) To: IEEE 802.3at throughout the data sheet ............................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION www.ti.com 1-Nov-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS23757PWR Package Package Pins Type Drawing TSSOP PW 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 7.1 1.6 8.0 W Pin1 (mm) Quadrant 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 1-Nov-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS23757PWR TSSOP PW 20 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.