TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 HIGH-POWER, WIDE VOLTAGE RANGE, QUAD-PORT ETHERNET POWER SOURCING EQUIPMENT MANAGER FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • • Quad-Port Power Management With Integrated Switches and Sense Resistors High Power PoE up to 25 W at PD Input Operating from a 53-V Minimum Input Power Rail Wide Range Single Supply: 21.5 V up to 57 V ICUT = 615 mA, ILIM = 650 mA Nominal IEEE 802.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 DESCRIPTION (CONTINUED) The TPS23841 has three internal supply buses (10 V, 6.3 V and 3.3 V) generated from the 48-V input supply. These supplies are used to bias all internal digital and analog circuitry. Each supply has been brought out separately for proper bypassing to insure high performance. The digital supply (3.3 V) is available for powering external loads up to 2 mA.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) PARAMETER VALUE UNIT V10 current sourced 100 µA V3.3 current sourced 5 mA Applied voltage on CINT#, CT, RBIAS –0.5 to 10 Applied voltage on SCL, SDA_I, SDA_O, INTB, A1, A2, A3, A4, A5, MS, PORB, WD_DIS, ALT_A/B, AC_LO, AC_HI –0.5 to 6 V Applied voltage on V48, P#, N# –0.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 ELECTRICAL CHARACTERISTICS V48 = 48 V, RT = 124 kΩ, CT = 220 pF, CINT = 0.027 µF (low leakage), –40°C to 125°C and TA = TJ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 4 9 12 10 14 UNIT Power Supply V48 quiescent current Off mode (all ports) V48 quiescent current Powered mode (all ports) V10, internal analog supply ILOAD = 0 9.75 10.5 11.5 V3.3, internal digital supply ILOAD = 0 to 3 mA 3 3.3 3.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 ELECTRICAL CHARACTERISTICS (continued) V48 = 48 V, RT = 124 kΩ, CT = 220 pF, CINT = 0.027 µF (low leakage), –40°C to 125°C and TA = TJ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Port Legacy Detection Legacy current limit P = N = 48 V Legacy voltage A/D conversion scale factor 100 mV < VPORT < 17.5 V Legacy A/D conversion time 0 V < VPORT < 15 V 2.6 3.5 4.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 ELECTRICAL CHARACTERISTICS (continued) V48 = 48 V, RT = 124 kΩ, CT = 220 pF, CINT = 0.027 µF (low leakage), –40°C to 125°C and TA = TJ (unless otherwise noted) PARAMETER Digital I2C TEST CONDITIONS MIN TYP MAX UNIT DC Specifications SCL, SDA_I, A1–A5 ,WD_DIS, ALTA/B, MS, PORB logic input threshold 1.
TPS23841 www.ti.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 TERMINAL FUNCTIONS TERMINAL NAME NO. PAP I/O DESCRIPTION PJD POWER AND GROUND V48 60 5 I 48-V input to the device. This supply can have a range of 22 V to 57 V. This pin should be decoupled with a 0.1-µF capacitor from V48 to AG1 placed as close to the device as possible. V10 58 7 O 10-V analog supply. The 10-V reference is generated internally and connects to the main internal analog power bus. A 0.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. PAP I/O DESCRIPTION PJD ANALOG SIGNALS This is a dual-purpose pin. When tied to an external capacitor this pin sets the internal clock. When the CT pin is grounded the SYN pin turns from a output to an input (see SYN pin description) CT 53 12 I The timing capacitor and the resistor on the RBIAS pin sets the internal clock frequency of the device.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 CONNECTION DIAGRAM TPS23841 64 Pin Power Pad TQFP_PAP 10 (1) NIC = No internal connection. Pins are floating. (2) NIC pins can be tied to the ground plane for improved thermal characteristics and to prevent noise injection from unused pins. (3) NIC pins next to CINT pins should be tied to ground to prevent noise injection into A/D converter.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 POWERPAD OUTLINE LASER MARKER PIN 1 IDENTIFIER TOP VIEW TPS23841 64 PIN POWER PAD UP TQFP - PJD (1) NIC = No internal connection. Pins are floating. (2) NIC pins can be tied to the ground plane for improved thermal characteristics and to prevent noise injection from unused pins. (3) NIC pins next to CINT pins should be tied to ground to prevent noise injection into A/D converter.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 AUTO MODE FUNCTIONAL DESCRIPTION Auto Mode Auto mode (AM, MS = 0) operation is the basic approach for applying power to IEEE compliant PD’s. When AM has been selected the TPS23841 automatically performs the following functions: • Discovery of IEEE 802.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 AUTO MODE FUNCTIONAL DESCRIPTION (continued) Auto Mode Functional Description Update Class Register PortPwr Update Reg OVI = Over Current Fault U/O V = Under or Over Voltage Fault TSD = Thermal Shutdown Fault TMPDO = PD Maintain Power Dropout Time Limit TED = Error Delay Timing A2D V/I Measurements 300 ms
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 AUTO MODE FUNCTIONAL DESCRIPTION (continued) AM Discovery The TPS23841 uses a four-point measurement technique using two low level probe signals (typically 4.4 V and 8.8V) during the discovery process to determine whether a valid PD is present. The use of a multipoint detection method for the PD resistor measurement allows accurate detection even when series steering diodes are present.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 AUTO MODE FUNCTIONAL DESCRIPTION (continued) AM Classification After a successful discovery of a valid PD the TPS23841 enters the classification function that identifies the power level based on the PD's current signature. The classification current level is measured at a reduced terminal voltage of 17.5V.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 AUTO MODE FUNCTIONAL DESCRIPTION (continued) Upon completion of classification the port classification register is updated. In AM mode this information is not used but for semi-auto mode the class information can be used for power management. Figure 4 shows actual class currents and the class assignment which were stored in the register. These assignments are compliant with the IEEE 802.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 AUTO MODE FUNCTIONAL DESCRIPTION (continued) AM Power Delivery After successfully discovery and classification of a valid PD the power is delivered by controlling the current to the PD until its current requirements are met or until the internal current limit is reached (approximately 650 mA). The power switch is fully enhanced after 500 µs.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 AUTO MODE FUNCTIONAL DESCRIPTION (continued) Over/Under Voltage Fault For the TPS23841, port over and undervoltge detection is disabled by default after device POR. This continuous voltage monitoring feature can subsequently be enabled by writing a logic 1 to bit D2 in the Common Control register, assuming usage under the direction of a higher level controller, (i.e., usage in semi-auto mode).
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 AUTO MODE FUNCTIONAL DESCRIPTION (continued) Over Current or Current Limit Faults Over current or current limit faults are conditions when the load current that is being sensed trips either the ICUT comparator (570 mA to 665 mA) or the ILIM comparator (600 mA to 700 mA) and turns on the current fault timer.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 AUTO MODE FUNCTIONAL DESCRIPTION (continued) Under Current Fault (DC Modulated Disconnect) Under current fault (dc modulated disconnect) is a condition when the load current that is being measured drops below 7.5mA and turns on the disconnect timer.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION Power Management Mode (PMM) Power management mode (PMM) has been designed to work efficiently with simple low-cost microcontrollers such as those in the MSP430 family. The power management mode uses 13 self-contained functions to completely control the device operation. You simply write/read through the I2C pins and wait for the function done bit to be set.
Set Done Bit Wait for Next Function Call Apply 8.8V (Imax5mA) To Chnl 4 ms Delay Start A2D Measure Chnl I (18mS) Store Value Discovery I Reg Set Done Bit Wait for Next Function Call Apply 4.4V (Imax5mA) To Chnl 4mSDelay Start A2D Measure Chnl I (18mS) Store Value Discovery I Reg Set Done Bit Wait for Next Function Call Enable Control Enable Control Power Down Reset all Functions Discover 2 0010 Discover 1 0001 Disable 0000 Figure 9.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION (continued) PMM Discovery 1 PMM Discovery 1 function waveforms for the N and CINT pins are shown in Figure 10. The measurement is being performed using 25 kΩ impedance between the P and N pin. The Discovery 1 voltage is allowed to settle for approximately 5ms before the A/D begins integrating. The voltage on the CINT pin shows the A/D cycle.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION (continued) PMM Discovery 2 PMM Discovery 2 function waveforms for the N and CINT pins are shown in Figure 11. Again the measurement is being performed using 25 kΩ impedance between the P and N pin. The Discovery 2 function was called after a Discovery 1 function so the voltage ramps from 4.4 V to 8.8 V below the P pin.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION (continued) PMM Legacy PMM Legacy function is used to detect PDs that are non compliant. Legacy detection uses a current source (typically 3.5 mA) as a test current while the A/D measures the average voltage for approximately 18 ms. The waveform shown in Figure 12 is the Legacy function charging a 10-µF capacitor.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION (continued) PMM Rup Pwr PMM Rup Pwr function turns on the port power by ramping up the current that is being delivered to the load in a controlled fashion. The output current ramps from 0 mA to ILIM (typically 650 mA) in approximately 500 µs. Figure 14 shows the output voltage and current turning on for a 250-mA load. Figure 14.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION (continued) Miscellaneous Functional Description PMM Faults PMM faults are the same as those shown in the AM Faults and INTB Output section. In PM mode, the port under- and over voltage and under-current faults can be enabled or disabled by writing to the control bits in the appropriate register.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION (continued) 2 I C Interface Description The serial interface used in the TPS23841 is a standard 2-wire I2C slave architecture. The standard SDA line of the I2C architecture is broken out into independent input and output data paths. This feature simplifies earth grounded controller applications that require opto-isolators to keep the 48-V return of the Ethernet power system floating.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION (continued) Start/Stop The high-to-low transition of SDA_I while SCL is high defines the start condition. The low to high transition of SDA_I while SCL is high defines the stop condition. The master device initiates all start and stop conditions. The first serial packet is enclosed within start and stop bits, consists of a 7-bit address field, read/write bit, and the acknowledge bit.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 POWER MANAGEMENT MODE FUNCTIONAL DESCRIPTION (continued) Chip Addressing Table 1 shows the bit assignments during the addressing cycle. Table 1. Address Selection Field BIT FUNCTION A7 Future expansion (value not compared) A6 Future expansion (value not compared) A5 Device address. Compared with pin A5 A4 Device address. Compared with pin A4 A3 Device address. Compared with pin A3 A2 Device address.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 Data Read Cycles For a data read sequence, after the register acknowledge bit, the master device generates a stop condition. This is followed by a second start condition, and re-transmitting the device address as described in chip address above. For this cycle, however, the R/W bit is set to a 1 to signal the read operation. The TPS23841 again responds with an acknowledge pulse.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 Table 3.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 Table 5.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 Table 7. Port Control Write 2, Register Select = 0011 (One Per Port) BIT (1) FUNCTION STATE PRESET STATE D7 Unused 0 0 D6 Unused 0 0 D5 Unused 0 0 0 = normal 1 = port disable 0 Enable (1) D4 Port D3 A/D Start 0 = normal 1 = start A/D (self clearing) 0 D2 A/D Abort 0 = normal 1 = abort 0 D1 Unused 0 0 D0 Unused 0 0 Consult factory for alternative B, semi-auto mode implementations which write to bit D4.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 Table 9.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 Table 12. Voltage — Lower Bits, Register Select = 1000 (One Per Port) BIT FUNCTION D7 A/D bit 7 D6 A/D bit 6 D5 A/D bit 5 D4 A/D bit 4 D3 A/D bit 3 D2 A/D bit 2 D1 A/D bit 1 D0 A/D bit 0 STATE A/D lower bits PRESET STATE 0 Table 13.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 Table 15. Current — Upper Bits, Register Select = 1011 (One Per Port) BIT FUNCTION STATE PRESET STATE D7 Current measurement complete 0 = measurement active (bit set low when A/D begins a current measurement) 1 = measurement complete (bit set high after A/D has completed a current measurement) 0 D6 A/D bit 14 A/D upper bits 0 D5 A/D bit 13 D4 A/D bit 12 D3 A/D bit 11 D2 A/D bit 10 D1 A/D bit 9 D0 A/D bit 8 Table 16.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 TPS23841 AC Drive Application Schematic Figure 17.
TPS23841 www.ti.
TPS23841 www.ti.com SLUS745A – NOVEMBER 2006 – REVISED MAY 2007 TPS23841 Basic 4-Port (PMM) Isolated Configuration with AC Disconnect TPS23841 basic 4-port isolated configuration with AC Disconnect (PAP pinout shown). Function 7.5K Auto 68uF + 0.1uF 220pF 124K 0.1uF 0.1uF 0.1uF - 7.5K 7.5K 7.5K SYN AC_HI AC_LO Ct V2.5 RG Rbias AG1 V48 V6.3 V10 MS RJ45-5 Xformer 1 2 48 3 46 47 CINT4 45 RET4 44 4 CINT1 0.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS23841PAPR HTQFP PAP 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 TPS23841PJDR HTQFP PJD 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS23841PAPR HTQFP PAP 64 1000 367.0 367.0 45.0 TPS23841PJDR HTQFP PJD 64 1000 367.0 367.0 45.
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