Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - hot swap controller -48 V TSSOP 14 Surface-mount





SLUS536C − AUGUST 2002 − REVISED AUGUST 2004

 

   

FEATURES

D Wide Input Supply Range: −20 V to −80 V

D Transient Rating to −100 V

D Programmable Current Limit

D Programmable Current Slew Rate

D Programmable UV/OV Thresholds/Hysteresis

D Debounced Insertion Detection Inputs

D Open-Drain Power Good (PG) Output

D Fault Timer to Eliminate Nuisance Trips

D Open-Drain Fault Output (FAULT)

D Enable Input (EN)

D 14-Pin TSSOP package

D 44-Pin TSSOP Package for

Creapage/Clearance

APPLICATIONS

D −48-V Distributed Power Systems

D Central Office Switching

D Wireless Base Station

DESCRIPTION

The TPS2392 and TPS2393 integrated circuits are hot

swap power managers optimized for use in nominal

−48-V systems. They operate with supply voltage

ranges from −20-V to −80-V, and are rated to withstand

spikes to −100 V. In conjunction with an external

N-channel FET and sense resistor, they can be used to

enable live insertion of plug-in cards and modules in

powered systems. Each device provides load current

slew rate control and peak magnitude limiting.

Undervoltage and overvoltage shutdown thresholds

are easily programmed via a three-resistor divider

network. In addition, two active-low, debounced inputs

provide plug-in insertion detection. A power good (PG)

output enables downstream converters. The TPS2392

and TPS2393 also provide the basic hot swap functions

of electrical isolation of faulty cards, filtered protection

against nuisance overcurrent trips, and single-line fault

reporting. The 44-pin part supports designs where

telecomm creepage and clearance requirements must

be followed.

The TPS2392 latches off in response to current faults,

while the TPS2393 periodically retries the load in the

event of a fault.

UDG−02098

BAS19

0.1 µF

3.92 kΩ

4.99 kΩ

200 kΩ

20 mΩ

1/4, 1%

10 kΩ

100

kΩ

100 µF

100 V

OUT

= 32.8 V

= 30.8 V

= 72.6 V

GATE

UVLO

INSA

INSB

FAULT

FLTTIME

OVLO

DRAINSNS

ISENS

IRAMP −VIN

RTN

TPS2392/TPS2393

VOUT+

VOUT−

VIN+

VIN−

DC/DC

CONVERTER

1500 pF

VOUT+

VOUT−

GND

3900 pF

−48V

IRF530

5.6 V

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

www.ti.com

Summary of content (33 pages)

PAGE 1
www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 FEATURES D D D D D D D D D D D D DESCRIPTION Wide Input Supply Range: −20 V to −80 V The TPS2392 and TPS2393 integrated circuits are hot swap power managers optimized for use in nominal −48-V systems. They operate with supply voltage ranges from −20-V to −80-V, and are rated to withstand spikes to −100 V.
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www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Input supply voltage, −VIN to RTN −80 −20 V Operating junction temperature, TJ −40 85 °C DISSIPATION RATINGS PACKAGE TA < 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 85°C POWER RATING TSSOP−14 750 mW 7.
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www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 ELECTRICAL CHARACTERISTICS VI(−VIN) = −48 V with respect to RTN, VI(EN) = 2.8 V, VI(INSA) = 0 V, VI(INSB) = 0 V, VI(UVLO) = 2.
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www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 ELECTRICAL CHARACTERISTICS (continued) VI(−VIN) = −48 V with respect to RTN, VI(EN) = 2.8 V, VI(INSA) = 0 V, VI(INSB) = 0 V, VI(UVLO) = 2.
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www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 PIN ASSIGNMENTS DRAINSNS: Sense input for monitoring the load voltage status. The DRAINSNS pin determines the load status by sensing the voltage level on the external pass FET drain. DRAINSNS must be pulled low with repect to −VIN (less than 1.35 V typically) to declare a power good condition. This corresponds to a low VDS across the FET, indicating that the load voltage has successfully ramped up to the DC input level.
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www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 PIN ASSIGNMENTS ISENS: Current sense input. An external low-value resistor connected between this pin and −VIN is used to feed back current magnitude information to the TPS2392 and TPS2393. There are two internal device thresholds associated with the voltage at the ISENS pin. During ramp-up of the load’s input capacitance, or during other periods of excessive demand, the HSPM acts to limit this voltage to 40 mV.
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www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 TYPICAL CHARACTERISTICS EN (5 V/div) EN (5 V/div) VDRAIN (20 V/div) VDRAIN (50 V/div) CONTACT BOUNCE CONTACT BOUNCE CIRAMP = 3900 pF CFLT = 0.1 µF CLOAD = 50 µF ILOAD (500 mA/div) CLOAD = 100 µF t − Time − 2.5 ms / div t − Time − 1 ms / div Figure 1. Live Insertion Event − VIN = −48 V Figure 2.
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www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 TYPICAL CHARACTERISTICS CLOAD = 50 µF VUVLO_L VUVLO_H RTN (5 V/div) RTN (5 V/div) GATE (5 V/div) GATE (5 V/div) CLOAD = 50µF RLOAD = 1 kΩ t − Time − 5 ms / div t − Time − 5 ms / div Figure 5. UVLO Protection, Supply Rising Figure 6. UVLO Protection Supply Falling IRAMP (2 V/div) INSA (5 V/div) CIRAMP= 3900 pF Insertion Delay GATE (5 V/div) CIRAMP = .022 µF CIRAMP = .056 µF CFLT = 0.
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www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 TYPICAL CHARACTERISTICS FAULT (50 V/div) FAULT (50 V/div) CIRAMP = 3900 pF CFLT = 0.047 µF CLOAD = 100 µF RLOAD = 12.5 Ω PG (50 V/div) CIRAMP = 3900 pF CFLT = 0.047 µF CLOAD = 100 µF PG (50 V/div) FLTTIME (2 V/div) FLTTIME (2 V/div) VDRAIN (50 V/div) VDRAIN (50 V/div) ILOAD (1 A/div) ILOAD (1 A/div) t − Time − 50 ms / div t − Time − 50 ms / div Figure 9. Fault Retry Operation (TPS2393) Figure 10.
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www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs AMBIENT TEMPERATURE 1500 CIRAMP = 6800 pF CLOAD = 50 µF VTH_PG VRTN = 80 V ICC − Supply Current − µA 1200 IRAMP (2 V/div) VDRAIN (20 V/div) 900 VRTN = 48 V 600 VRTN = 36 V VRTN = 20 V 300 PG (50 V/div) 0 −40 t − Time − 1 ms / div −15 10 35 60 TA − Ambient Temperature − °C Figure 13.
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www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 TYPICAL CHARACTERISTICS IRAMP OUTPUT CURRENT vs AMBIENT TEMPERATURE, NORMAL RATE −47 −9.0 VI(ISENS) = 80 mV VO(FLTTIME) =2V Average for VO(IRAMP) = 1 V, 3 V VRTN = 20 V to 80 V −48 ICHG − Charging Current − µA ISRC2 − IRAMP Output Current − µA TIMER CHARGING CURRENT vs AMBIENT TEMPERATURE −9.4 −9.8 −10.2 VRTN = 20 V −49 −50 −51 VRTN = 36 V −10.6 VRTN = 48 V VRTN = 80 V −52 −11.
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www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 TYPICAL CHARACTERISTICS UVLO PIN PULL-UP CURRENT vs AMBIENT TEMPERATURE VOLTAGE COMPARATOR THRESHOLD vs AMBIENT TEMPERATURE −9.3 ISRC_UV − Charging Current − µA VTH − Voltage Comparator Threshold − V 1.44 VI(RTN) = 20 V to 48 V Undervoltage Comparator 1.42 1.40 Overvoltage Comparator VI(RTN) = 80 V 1.38 VI(UVLO) = 2.5 V VI(RTN) = 20 V to 48 V −9.5 −9.7 −9.9 −10.1 1.
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www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 DETAILED DESCRIPTION When a plug-in module or printed circuit card is inserted into a live chassis slot, discharged supply bulk capacitance on the board can draw huge transient currents from the system supplies. Without some form of inrush limiting, these currents can reach peak magnitudes ranging over 100 A, particularly in high-voltage systems.
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www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 DETAILED DESCRIPTION RTN 11 10 µA 10 µA 1.35V 13 DRAINSNS 12 PG + + INSA 2 + 10 µA Q R Q 5V + INSB S FLT 3 10 µA EN_A H=CLOSED UVLO 1 7 IRAMP 4 FAULT 6 FLTTIME 9 ISENS 10 GATE RAMP GENERATOR + VLIM FLT ON 10 µA L=CLOSED EN OVLO 14 FAULT TIMER + OC 10 µA 5 Q R R Q FT OVERCURRENT 100 mV OLC + + VLIM 1.4V −VIN S OVERLOAD H=CLOSED EN OL S LCA + EN_A 8 UDG−02116 Figure 24.
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www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 RTN 34 10 µA 10 µA 1.35V 41 DRAINSNS 40 PG + + INSA 1 + 10 µA Q R Q 5V + INSB S FLT 7 10 µA EN_A H=CLOSED UVLO 44 16 IRAMP RAMP GENERATOR + VLIM FLT 13 ON 10 µA L=CLOSED EN OVLO 43 FAULT TIMER + OC OL S S Q R R Q FAULT FT 15 FLTTIME 10 µA OVERLOAD OVERCURRENT H=CLOSED EN 14 27 ISENS + VLIM 1.4V −VIN 100 mV OLC + LCA + 28 GATE EN_A 22 UDG−02116 Figure 25.
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www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 DETAILED DESCRIPTION Current fault response timing and retry duty cycle are accomplished by the fault timer block in conjunction with an external capacitor connected between the FLTTIME and −VIN pins. Whenever the hot swap controller is in current control mode, such as during inrush limiting at insertion, or in response to excessive demand during operation of the plug-in, the LCA asserts the OVERCURRENT signal shown in Figure 24.
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www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 DETAILED DESCRIPTION 10 µA 600 nA SLOW + 0.5 V IRAMP VLIM 99R EN_A R 40mV UDG−20117 Figure 26. Ramp Generator Block Details Note that any condition which causes turn-off of the external FET (EN_A signal goes low) also causes a rapid discharge of the IRAMP capacitor. In this manner, the soft-start function is automatically reset by the TPS2392 and TPS2393, and ready for the next load enable event.
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www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 DETAILED DESCRIPTION 4 µs OL 50 µA FAULT S 4V OC S Q R Q + FLTTIME 0.4 µA RETRY 0.5V + RESET ON EN FAULT LOGIC R TPS2393 ONLY See block diagram on page 15 and 16 for pinout. UDG−20118 Figure 27. Fault Timer Block Operation Note that because of the timing inhibit during the initial slow ramp period, the duty cycle in practice is slightly greater than the nominal 1% value.
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www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 APPLICATION INFORMATION setting the sense resistor value Due to the current−limiting action of the internal LCA, the maximum allowable load current for an implementation is easily programmed by selecting the appropriate sense resistor value. The LCA acts to limit the sense voltage VI(ISENS) to its internal reference. Once the voltage at the IRAMP pin exceeds approximately 4 V, this limit is the clamp voltage, VREF_K.
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www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 APPLICATION INFORMATION setting the fault timing capacitor The fault timeout period is established by the value of the capacitor connected to the FLTTIME pin, CFLT. The timeout period permits riding out spurious current glitches and surges that may occur during operation of the system, and prevents indefinite sourcing into faulted loads swapped into a live system.
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www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 APPLICATION INFORMATION With this information, the minimum recommended value timing capacitor CFLT can be determined. The delay time needed will be either tSS or the sum of tSS and tCC, according to the estimated time to charge the load. Since fault timing is generated by the constant-current charging of CFLT, the capacitor value is determined by equation (6) or (7). C FLT(min) + C FLT(min) + 55 t SS 3.75 55 (6) ǒt SS ) t CCǓ 3.
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www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 APPLICATION INFORMATION The UV and OV thresholds can be individually programmed with a three-resistor divider connected to it as shown in the typical application diagram, and again in Figure 27a. When the desired trip voltages and undervoltage hysteresis have been established for the protected board, the resistor values needed can be determined from the following equations.
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www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 APPLICATION INFORMATION using the PG output The PG output is an indication of the load power status. PG is asserted after a load turn-on, once the load voltage has ramped up to the input dc level, as indicated by a small VDS drop across the pass FET. The load voltage is sensed by the DRAINSNS pin, which is connected to the pass FET drain through a small-signal blocking diode.
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www.ti.com SLUS536C − AUGUST 2002 − REVISED AUGUST 2004 APPLICATION INFORMATION If the selected converter cannot tolerate any voltage excursions below VIN− potential, an alternative is to drive the enable through an optocoupler. An implementation is shown in Figure 29. DC/DC CONVERTER VIN+ VOUT+ GND VDD R7 CIN EN VIN− RTN PG TPS2392* TPS2393* 10 µA VOUT− D1 BAS19 DRNSNS Q1 GATE −VIN ISENS RSENSE −48 V *Additional details omitted for clarity.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 10-Jun-2014 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 6-Dec-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS2392PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TPS2393PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 6-Dec-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2392PWR TSSOP PW 14 2000 367.0 367.0 35.0 TPS2393PWR TSSOP PW 14 2000 367.0 367.0 35.
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