Datasheet

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PGb

TIMER

GND

VCC

SENSE

GATE

OUT

DGK Package

(Top View)

TPS2470x

2 m

SENSE

CSD16403Q5

OUT

GATESENSE

PGb

TIMER

GND

18.7

kΩ

130 k

OUT

3.01 kΩ

VCC

UVLO

LMT

FAULT

= 10.8 V

I = 12 A

t = 7.56 ms

3 V

GATE

10 Ω

0.1 Fμ

OUT

470 Fμ

56 nF

TPS24700

TPS24701

www.ti.com

SLVSAL3B – MARCH 2011– REVISED MAY 2011

2.5-V to 18-V High-Efficiency Hot-Swap Controller

Check for Samples: TPS24700, TPS24701

FEATURES

APPLICATIONS

• 2.5-V to 18-V Operation • Server Backplanes

• Accurate Current Limiting for Starup • Storage Area Networks (SAN)

• Accurate 25-mV Current Sense Threshold • Medical Systems

• Timed Overcurrent Breaker • Plug-In Modules

• Power-Good Output • Base Stations

• Fast Breaker for Short-Circuit Protection • Consumer Electronics

• Latch Off (TPS24700) and Retry Versions

(TPS24701)

• Programmable UV Threshold

• Drop-In Upgrade for LTC4211 – No Layout

Changes

• Small MSOP-8 Package

DESCRIPTION

The TPS24700/1 is an easy-to-use, 2.5 V to 18 V, hot-swap controller that drives an external N-channel

MOSFET. The programmable current limit and fault time protect the supply and load from excessive current at

startup. After startup, currents above the user-selected limit are allowed to flow until programmed timeout –

except in extreme overload events when load is immediately disconnected from source. The low, 25-mV current

sense threshold is highly accurate and allows use of smaller, more-efficient sense resistors, yielding lower power

loss and smaller footprint. A power-good output is provided for status monitoring and downstream load control.

TPS24700/1 replaces the LTC4211 in existing designs with no PCB board changes and only minor external

component changes – yielding a more accurate, efficient solution.

Text for Spacing Text for Spacing

TYPICAL APPLICATION OF TPS24700/1 (12 V AT 10 A) PINOUT

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (31 pages)

PAGE 1
TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com 2.5-V to 18-V High-Efficiency Hot-Swap Controller Check for Samples: TPS24700, TPS24701 FEATURES APPLICATIONS • • • • • • • • • • • • • 1 • • • 2.
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TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN Input voltage range Sink current External capacitance SENSE, VCC MAX 2.5 18 EN, PGb, OUT 0 18 PGb 0 2 TIMER 1 GATE UNIT V mA nF (1) –40 Operating junction temperature range, TJ (1) NOM 1 µF 125 °C External capacitance tied to GATE should be in series with a resistor no less than 1 kΩ.
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TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) –40°C ≤ TJ ≤ 125°C, VCC = 12 V, and VEN = 3 V. All voltages referenced to GND, unless otherwise noted. PARAMETER CONDITIONS MIN Fast turnoff, VGATE = 14 V Sinking current Sustained, VGATE = 4 V to 23 V NOM MAX UNIT 0.5 1 1.
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TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM M1 VIN RSENSE SENSE RGATE GATE OUT 6 7 5 60 mV DC + Charge Pump – RSET VCC – Servo Amplifier Fast Comparator Summing Point Inrush Latch + 30 µA + 8 Gate Comparator – VCC 6V 11 mA 1-shot S Q R Q + – 0~60 µA RIMON + 675 mV – Main Opamp in Inrush Limit Becomes Comparator After Inrush Limit Complete 2.32 V 2.
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TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com DETAILED PIN DESCRIPTIONS The following description relies on the typical application diagram shown on the front page of this data sheet, as well as the functional block diagram of Figure 4. EN: Applying a voltage of 1.35 V or more to this pin enables the gate driver. The addition of an external resistor divider allows the EN pin to serve as an undervoltage monitor.
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TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com A fast-trip shutdown occurs when V(VCC–VSENSE) exceeds 60 mV. TIMER: A capacitor CT connected from the TIMER pin to GND determines the overload fault timing. TIMER sources 10 μA when an overload is present, and discharges CT at 10 μA otherwise. M1 is turned off when VTIMER reaches 1.35 V. In an application implementing auto-retry after a fault, this capacitor also determines the period before the external MOSFET is re-enabled.
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TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com TYPICAL CHARACTERISTICS 1200 5 T = 125°C T = 25°C Supply Current (µA) Supply Current (µA) 1000 4 T = 125°C 800 T = –40°C T = 25°C 3 2 T = –40°C 600 1 400 0 4 2 6 8 10 12 14 Input Voltage, VVCC (V) 16 18 0 20 Figure 5. Supply Current vs Input Voltage at Normal Operation (EN = High) 4 2 6 8 10 12 14 Input Voltage, VVCC (V) 16 18 20 Figure 6. Supply Current vs Input Voltage at Shutdown (EN = 0 V) 40 26.
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TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com 7 32 TIMER Activation Voltage Threshold (V) Gate Voltage Referenced to GND, VGATE (V) TYPICAL CHARACTERISTICS (continued) T = 25°C 28 T = 125°C 24 20 T = –40°C 16 12 8 4 0 8 12 Input Voltage, VVCC (V) 16 T = 125°C 6 T = –40°C 5 4 3 20 Figure 11. Gate Voltage With Zero Gate Current vs VVCC 8 12 Input Voltage, VVCC (V) 16 20 2.36 VVCC = 12 V VVCC = 12 V EN Upper Threshold 1.
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TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com 160 0.7 VEN = 0 V 140 120 VVCC = 18 V VVCC = 2.5 V 100 80 60 –50 –20 10 40 70 Temperature (°C) 100 0.2 130 T = –40°C 4 0 8 12 Input Voltage, VVCC (V) 16 20 Figure 18. Supply Current vs VVCC and Temperature When EN Pulled Low 0.365 Timer Lower Threshold Voltage (V) Timer Upper Threshold Voltage (V) 0.4 0.3 1.344 1.342 VVCC = 18 V VVCC = 12 V 1.34 1.338 VVCC = 2.5 V 1.336 1.
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TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com SYSTEM OPERATION INTRODUCTION The TPS24700/1 provides all the features needed for a positive hot-swap controller.
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TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com INRUSH OPERATION When the TPS2470/1 activates MOSFET M1, a current flows into the downstream bulk storage capacitors. When this current exceeds the limit threshold set by Equation 1, the gate of the MOSFET is regulated by a feedback loop to make the MOSFET current stay at a current level no more than the current limit threshold. This limits the inrush current charging capacitance.
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TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com Figure 24. Circuit-Breaker Mode During Overload Condition M1 ILIMIT RSENSE RGATE VCC 8 RSET SENSE GATE 7 6 + 60 mV + A1 – – Server Amplifier Fast Trip Comparator 60 μA + 675 mV 30 μA VCP A2 – Current Limit Amp RIMON B0439-03 Figure 25.
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TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com Figure 26. Current Limit During Output Load Short-Circuit Condition (Overview) Figure 27. Current Limit During Output-Load Short-Circuit Condition (Onset) AUTOMATIC RESTART The TPS24701 automatically initiates a restart after a fault has caused it to turn off the external MOSFET M1.
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TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com Internal control circuits use CT to count 16 cycles before re-enabling M1 as shown in Figure 28. This sequence repeats if the fault persists. The timer has a 1 : 1 charge-to-discharge current ratio. For the very first cycle, the TIMER pin starts from 0 V and rises to the upper threshold of 1.35 V and subsequently falls to 0.35 V before restarting. For the following 16 cycles, 0.35 V is used as the lower threshold.
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TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com Figure 29. Latch After Overload Fault PGb AND TIMER OPERATIONS The open-drain PGb output provides a deglitched end-of-inrush indication based on the voltage across M1. PGb is useful for preventing a downstream dc/dc converter from starting while its input capacitor COUT is still charging. PGb goes active-low about 3.4 ms after COUT is charged.
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TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com • • In an overload fault, TIMER begins to source current to the timer capacitor, CT, when the load current exceeds the programmed current limits. When the timer capacitor voltage reaches its upper threshold of 1.35 V, TIMER begins to sink current from the timer capacitor, CT, and the GATE pin is pulled to ground. After the fault timer period, TIMER may go into latch mode (TPS24700) or retry mode (TPS24701).
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TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com DESIGN EXAMPLE: CURRENT-LIMITED START-UP This design example assumes a 12-V system voltage with an operating tolerance of ±2 V. The rated load current is 10 A, corresponding to a dc load of 1.2 Ω. If the current exceeds 12 A, then the controller should shut down and then attempt to restart. Ambient temperatures may range from 20°C to 50°C. The load has a minimum input capacitance of 470 μF.
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TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com Next select the on resistance of the transistor, rDS(on). The maximum on-resistance must not generate a voltage greater then the minimum power-good threshold voltage of 140 mV. Assuming a current limit of 12 A, a maximum rDS(on) of 11.67 mΩ is required. Also consider the effect of rDS(on) upon the maximum operating temperature TJ(MAX) of the MOSFET. Equation 4 computes the value of rDS(on)(MAX) at a junction temperature of TJ(MAX).
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TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com CSD16403Q5 SOA curve at TJ = 25°C, the MOSFET can tolerate 12 A with 12 V across it for approximately 20 ms. If the junction temperature TJ is other than 25°C, then the pulse time should be scaled by a factor of (150°C – TJ) / (150°C – 25°C). Therefore, the fault timer should be set between 1.08 ms and 20 ms.
PAGE 21
TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com The TPS24700/1 can be used in applications that expect a constant inrush current. This current is controlled by a capacitor connected from the GATE terminal to GND. A resistor of 1 kΩ placed in series with this capacitor prevents it from slowing a fast-turnoff event. In this mode of operation, M1 operates as a source follower, and the slew rate of the output voltage approximately equals the slew rate of the gate voltage (see Figure 32).
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TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com Gate voltage overstress and abnormally large fault current spikes can be caused by large gate capacitance. An external gate clamp Zener diode is recommended to assist the internal Zener if the total gate capacitance of M1 exceeds about 4000 pF. When gate capacitor dV/dt control is used, a 1-kΩ resistor in series with CG is recommended.
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TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com LOAD CURRENT PATH LOAD CURRENT PATH SENSE VCC SENSE VCC RSENSE TPS2470x TPS2470x Method 1 Method 2 M0217-03 Figure 33.
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TPS24700 TPS24701 SLVSAL3B – MARCH 2011 – REVISED MAY 2011 www.ti.com REVISION HISTORY Changes from Revision Original (April 2011) to Revision A • Revised voltage values shown in the block diagram ............................................................................................................ 5 Changes from Revision A (April 2011) to Revision B • 24 Page Page Changed in DETAILED PIN DESCRIPTIONS - PGb: from 140mV / 340mV to 170mV / 240 mV ......................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 12-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS24700DGKR Package Package Pins Type Drawing VSSOP DGK 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 12-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS24700DGKR VSSOP DGK 8 2500 364.0 364.0 27.
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