TPS24720 www.ti.com SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 2.5-V to 18-V High-Efficiency Adjustable Power-Limiting Hot-Swap Controller With Current Monitor and Overvoltage Protection Check for Samples: TPS24720 FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • 1 2.
TPS24720 SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
TPS24720 www.ti.com SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN ENSD, OV NOM MAX UNIT 0 16 2.5 18 EN, FFLTb, FLTb, PGb, OUT 0 18 Sink current FFLTb, FLTb, PGb 0 2 mA Source current IMON 0 1 mA Resistance PROG 4.
TPS24720 SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) –40°C ≤ TJ ≤ 125°C, VCC = 12 V, VEN = 3 V, VENSD = 3 V, RSET = 190 Ω, RIMON = 5 kΩ, and RPROG = 50 kΩ to GND. All voltages referenced to GND, unless otherwise noted. PARAMETER CONDITIONS Output low voltage Sinking 2 mA Input leakage current VPGb = 0 V, 30 V Delay (deglitch) time Rising or falling edge MIN NOM MAX UNIT 0.11 0.25 V –1 0 1 µA 2 3.
TPS24720 www.ti.com SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 ELECTRICAL CHARACTERISTICS (continued) –40°C ≤ TJ ≤ 125°C, VCC = 12 V, VEN = 3 V, VENSD = 3 V, RSET = 190 Ω, RIMON = 5 kΩ, and RPROG = 50 kΩ to GND. All voltages referenced to GND, unless otherwise noted. PARAMETER CONDITIONS MIN NOM MAX UNIT 0.3 0.9 1.
TPS24720 SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 www.ti.com FUNCTIONAL BLOCK DIAGRAM M1 VIN RSENSE RSET SET SENSE 11 7 RGATE GATE OUT 10 8 60 mV Charge Pump – + DC VCC – Servo Amplifier Fast Comparator – IMON RIMON Gate Comparator S Q R Q + VCC 5.9 V 11 mA 1-shot 6 Inrush Latch + 30 µA + 12 – 0~60 µA + A – 9 ö , 675 mV ÷ è B ø Main Opamp in Inrush FFLTb æ KpA Min ç + PROG RPROG OUT DC UVLO + 2.32 V 2.
TPS24720 www.ti.com SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 PIN FUNCTIONS (continued) NAME PIN I/O DESCRIPTION LATCH 14 I Latch or retry mode select input. Latch when floating or connected to a logic-level voltage; retry when connected to GND. OUT 8 I Output voltage sensor for monitoring MOSFET power. OV 5 I Overvoltage comparator input. Connects to resistor divider. GATE is pulled low when OV exceeds the threshold. PGb 15 O Active-low, open-drain power-good indicator.
TPS24720 SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 www.ti.com GATE: This pin provides gate drive to the external MOSFET. A charge pump sources 30 µA to enhance the external MOSFET. A 13.9-V clamp between GATE and VCC limits the gate-to-source voltage, because VVCC is very close to VOUT in normal operation. During start-up, a transconductance amplifier regulates the gate voltage of M1 to provide inrush current limiting. The TIMER pin charges timer capacitor CT during the inrush.
TPS24720 www.ti.com • • • • SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 VENSD is below its threshold. VVCC drops below the UVLO threshold. VOV is above its rising threshold. Die temperature exceeds the OTSD threshold. This pin can be left floating when not used. PROG: A resistor from this pin to GND sets the maximum power permitted in the external MOSFET M1 during inrush. Do not apply a voltage to this pin. If the constant power limit is not desired, use a PROG resistor of 4.99 kΩ.
TPS24720 SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 www.ti.com TIMER is not affected when the die temperature exceeds the OTSD threshold. VCC: This pin performs three functions. First, it provides biasing power to the integrated circuit. Second, it serves as an input to the power-on reset (POR) and undervoltage lockout (UVLO) functions. The VCC trace from the integrated circuit should connect directly to the positive terminal of RSENSE to minimize the voltage sensing error.
TPS24720 www.ti.com SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS 5 1200 T = 125°C 1000 T = 25°C Supply Current (µA) Supply Current (µA) 4 T = 125°C 800 T = –40°C T = 25°C 3 2 T = –40°C 600 1 400 0 4 2 6 8 10 12 14 Input Voltage, VVCC (V) 16 18 0 20 Figure 6. Supply Current vs Input Voltage at Normal Operation (EN = High) 0 4 2 6 8 10 12 14 Input Voltage, VVCC (V) 16 18 20 Figure 7. Supply Current vs Input Voltage at Shutdown (EN = 0 V) 32 26.
TPS24720 SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 www.ti.com 0.7 0.2 T = –40°C Gate Current (A) 0.6 0.15 T = 25°C 0.5 0.1 0.4 0.05 0.3 0 V(VCC – SENSE) T = 125°C 0.2 –0.05 0.1 –0.1 0 –0.15 –0.1 –0.2 VVCC = 3.3 V –0.2 –10 0 10 20 40 30 –0.25 Gate Voltage Referenced to GND, VGATE (V) 0.25 Voltage, V(VCC – SENSE) (V) TYPICAL CHARACTERISTICS (continued) 0.9 Time (µs) Figure 12. Gate Current During Fast Trip, VVCC = VGATE = 3.
TPS24720 www.ti.com SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 TYPICAL CHARACTERISTICS (continued) 64 PGb Rising Fast-Trip Threshold Voltage (mV) V(SENSE – OUT) Threshold Voltage (mV) 240 220 200 180 PGb Falling 160 140 –50 –20 10 40 70 Temperature (°C) 100 120 VVCC = 18 V VVCC = 2.5 V 100 80 VVCC = 12 V 60 –50 –20 10 40 70 Temperature (°C) 100 130 Figure 20. PGb Open-Drain Output Voltage in Low State 62 61.5 61 VVCC = 18 V 60.
TPS24720 SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 0.365 Timer Lower Threshold Voltage (V) Timer Upper Threshold Voltage (V) 1.344 1.342 VVCC = 18 V VVCC = 12 V 1.34 1.338 VVCC = 2.5 V 1.336 1.334 –50 –20 10 40 70 Temperature (°C) 100 Figure 24. Timer Upper Threshold Voltage vs Temperature at Various Input Voltages –20 10 40 70 Temperature (°C) 10.3 VVCC = 18 V Timer Sinking Current (µA) Timer Sourcing Current (µA) VVCC = 2.
TPS24720 www.ti.com SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 SYSTEM OPERATION INTRODUCTION The TPS24720 provides all the features needed for a positive hot-swap controller.
TPS24720 SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 www.ti.com Figure 29. Inrush Mode at Hot-Swap Circuit Insertion INRUSH OPERATION After TPS24720 initialization is complete (as described in the Board Plug-In section) and EN is active, GATE is enabled (VGATE starts increasing). When VGATE reaches the MOSFET M1 gate threshold, a current flows into the downstream bulk storage capacitors.
TPS24720 www.ti.com SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 dissipated within the MOSFET, labeled FET PWR, remaining substantially constant during this period of operation, which ends when the current through the MOSFET reaches the current limit ILIM.
TPS24720 SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 www.ti.com Figure 31. Circuit-Breaker Mode During Overload Condition ILIMIT M1 RSENSE RGATE RSET SET VCC 7 12 SENSE GATE 11 10 OUT 8 + 60 mV – Server Amplifier + – Fast Trip Comparator A1 60 μA + 675 mV IMON RIMON 6 PROG VCP – Current Limit Amp 2 RPROG A2 30 μA + B0439-01 Figure 32.
TPS24720 www.ti.com SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 Figure 33. Current Limit During Output-Load Short-Circuit Condition (Overview) Figure 34.
TPS24720 SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 www.ti.com AUTOMATIC RESTART If LATCH is connected to GND, then the TPS24720 automatically initiates a restart after a fault has caused it to turn off the external MOSFET M1. Internal control circuits use CT to count 16 cycles before re-enabling M1 as shown in Figure 35. This sequence repeats if the fault persists. The timer has a 1 : 1 charge-to-discharge current ratio.
TPS24720 www.ti.com SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 Figure 36.
TPS24720 SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 www.ti.com PGb, FLTb, AND TIMER OPERATIONS The open-drain PGb output provides a deglitched end-of-inrush indication based on the voltage across M1. PGb is useful for preventing a downstream dc/dc converter from starting while its input capacitor COUT is still charging. PGb goes active-low about 3.4 ms after COUT is charged. This delay allows M1 to fully turn on and any transients in the power circuits to end before the converter starts up.
TPS24720 www.ti.com SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 START-UP OF HOT-SWAP CIRCUIT BY VCC OR EN The connection and disconnection between a load and the input power bus are controlled by turning on and turning off the MOSFET, M1. The TPS24720 has two ways to turn on MOSFET M1: • Increasing VVCC above UVLO upper threshold while EN is already higher than its upper threshold sources current to the GATE pin. After an inrush period, the TPS24720 fully turns on MOSFET M1.
TPS24720 SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 www.ti.com PROTECTION RSENSE 0.1 μF LOAD M1 0.1 μF RSET RGATE Specifications (at Output): Peak Current Limit = 12 A Nominal Current = 10 A COUT 470 μF OUT GATE SENSE SET VCC 12-V Main Bus Supply RLOAD 1.2 W IMON GND TPS24720 RIMON TIMER CT B0440-01 Figure 37. Simplified Block Diagram of the System Constructed in the Design Example STEP 1.
TPS24720 www.ti.com SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 Next select the on-resistance of the transistor, rDS(on). The maximum on-resistance must not generate a voltage greater then the minimum power-good threshold voltage of 140 mV. Assuming a current limit of 12 A, a maximum rDS(on) of 11.67 mΩ is required. Also consider the effect of rDS(on) on the maximum operating temperature TJ(MAX) of the MOSFET. Equation 6 computes the value of rDS(on)(MAX) at a junction temperature of TJ(MAX).
TPS24720 SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 www.ti.com Power limit fold back (PLIM-FB) is the ratio of operating current limit (ILIM) and minimum power limited (regulated) current (when VOUT = 0 V). Degradation of programmed power limit (PLIM) accuracy and start up issues may occur if PLIM-FB is too large. Equation 9 calculates VSNS-PL_MIN (minimum sense voltage during power limit) and PLIM-FB. To ensure reliable operation, verify that PLIM-FB < 10 and VSNS,PL,MIN > 3 mV. P ´ RSENSE 29.
TPS24720 www.ti.com SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 For this example, select 7 ms to allow for variation of system parameters such as temperature, load, component tolerance, and input voltage. The timing capacitor is calculated in Equation 12 as 52 nF. Selecting the nexthighest standard value, 56 nF, yields a 7.56-ms fault time. 10 μA CT = ´ tFLT , 1.35 V therefore, CT = 10 μA ´ 7 ms = 52 nF 1.
TPS24720 SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 www.ti.com STEP 7. Choose RGATE, R4, R5, R6, and C1 In the typical application diagram on the front page, the gate resistor, RGATE, is intended to suppress highfrequency oscillations. A resistor of 10 Ω serves for most applications, but if M1 has a CISS below 200 pF, then 33 Ω is recommended. Applications with larger MOSFETs and very short wiring may not require RGATE.
TPS24720 www.ti.com SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 ADDITIONAL DESIGN CONSIDERATIONS Use of PGb Use the PGb pin to control and coordinate a downstream dc/dc converter. If this is not done, then a long time delay is needed to allow COUT to fully charge before the converter starts.
TPS24720 SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 www.ti.com Layout Considerations TPS24720 applications require careful attention to layout to ensure proper performance and to minimize susceptibility to transients and noise. In general, all traces should be as short as possible, but the following list deserves first consideration: • Decoupling capacitors on VCC pin should have minimal trace lengths to the pin and to GND.
TPS24720 www.ti.com SLVSAL1C – MARCH 2011 – REVISED SEPTEMBER 2013 REVISION HISTORY Changes from Original (March 2011) to Revision A • Page Corrected voltages shown in the block diagram ................................................................................................................... 6 Changes from Revision A (April 2011) to Revision B Page • Changed voltages in PGb pin description from 140 mV and 340 mV to 170 mV and 240 mV. ...........................................
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 31-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS24720RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS24720RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.
PACKAGE MATERIALS INFORMATION www.ti.com 31-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS24720RGTR QFN RGT 16 3000 367.0 367.0 35.0 TPS24720RGTT QFN RGT 16 250 210.0 185.0 35.
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