Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - gate drivers PWM High side, Low side, Sychronous SOIC 8

TPS28225

TPS28226

www.ti.com

SLUS710C –MAY 2006–REVISED APRIL 2010

High-Frequency 4-A Sink Synchronous MOSFET Drivers

Check for Samples: TPS28225, TPS28226

FEATURES

DESCRIPTION

• Drives Two N-Channel MOSFETs with 14-ns

Adaptive Dead Time

The TPS28225 and TPS28226 are high-speed

drivers for N-channel complimentary driven power

• Wide Gate Drive Voltage: 4.5 V Up to 8.8 V

MOSFETs with adaptive dead-time control. These

With Best Efficiency at 7 V to 8 V

drivers are optimized for use in variety of high-current

• Wide Power System Train Input Voltage: 3 V

one and multi-phase dc-to-dc converters. The

Up to 27 V

TPS28225/6 is a solution that provides highly

• Wide Input PWM Signals: 2.0 V up to 13.2-V

efficient, small size low EMI emmissions.

Amplitude

The performance is achieved by up to 8.8-V gate

• Capable Drive MOSFETs with ≥40-A Current

drive voltage, 14-ns adaptive dead-time control, 14-ns

per Phase

propagation delays and high-current 2-A source and

4-A sink drive capability. The 0.4-Ω impedance for

• High Frequency Operation: 14-ns Propagation

the lower gate driver holds the gate of power

Delay and 10-ns Rise/Fall Time Allow F

- 2

MOSFET below its threshold and ensures no

MHz

shoot-through current at high dV/dt phase node

• Capable Propagate <30-ns Input PWM Pulses

transitions. The bootstrap capacitor charged by an

• Low-Side Driver Sink On-Resistance (0.4 Ω)

internal diode allows use of N-channel MOSFETs in

half-bridge configuration.

Prevents dV/dT Related Shoot-Through

Current

The TPS28225/6 features a 3-state PWM input

• 3-State PWM Input for Power Stage Shutdown

compatible with all multi-phase controllers employing

3-state output feature. As long as the input stays

• Space Saving Enable (input) and Power Good

within 3-state window for the 250-ns hold-off time, the

(output) Signals on Same Pin

driver switches both outputs low. This shutdown

• Thermal Shutdown

mode prevents a load from the reversed-

• UVLO Protection

output-voltage.

• Internal Bootstrap Diode

The other features include under voltage lockout,

• Economical SOIC-8 and Thermally Enhanced

thermal shutdown and two-way enable/power good

signal. Systems without 3-state featured controllers

3-mm x 3-mm DFN-8 Packages

can use enable/power good input/output to hold both

• High Performance Replacement for Popular

outputs low during shutting down.

3-State Input Drivers

The TPS28225/6 is offered in an economical SOIC-8

and thermally enhanced low-size Dual Flat No-Lead

APPLICATIONS

(DFN-8) packages. The driver is specified in the

• Multi-Phase DC-to-DC Converters with Analog

extended temperature range of –40°C to 125°C with

or Digital Control

the absolute maximum junction temperature 150°C.

• Desktop and Server VRMs and EVRDs

The TPS28226 operates in the same manner as the

• Portable/Notebook Regulators

TPS28225/6 other than the input under voltage lock

• Synchronous Rectification for Isolated Power

out. Unless otherwise stated all references to the

Supplies

TPS28225 apply to the TPS28226 also.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains

PRODUCTION DATA information current as of publication date.

Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (38 pages)

PAGE 1
TPS28225 TPS28226 www.ti.com SLUS710C – MAY 2006 – REVISED APRIL 2010 High-Frequency 4-A Sink Synchronous MOSFET Drivers Check for Samples: TPS28225, TPS28226 FEATURES 1 • • • • • • • • • • • • • • • Drives Two N-Channel MOSFETs with 14-ns Adaptive Dead Time Wide Gate Drive Voltage: 4.5 V Up to 8.8 V With Best Efficiency at 7 V to 8 V Wide Power System Train Input Voltage: 3 V Up to 27 V Wide Input PWM Signals: 2.0 V up to 13.
PAGE 2
TPS28225 TPS28226 SLUS710C – MAY 2006 – REVISED APRIL 2010 www.ti.com FUNCTIONAL BLOCK DIAGRAM VDD 6 2 BOOT 1 UGATE 8 PHASE 5 LGATE 4 GND UVLO EN/PG 7 THERMAL SD SHOOTTHROUGH PROTECTION VDD HLD-OFF TIME 27K 3-STATE INPUT CIRCUIT PWM 3 13K TYPICAL APPLICATIONS One-Phase POL Regulator VDD (4.
PAGE 3
TPS28225 TPS28226 www.ti.com SLUS710C – MAY 2006 – REVISED APRIL 2010 TYPICAL APPLICATIONS (continued) Driver for Synchronous Rectification with Complementary Driven MOSFETs 12 V 35 V to 75V VOUT = 3.3 V Primary High Side VDD High Voltage Driver HB PWM CONTROLLER LI DRIVE HI C O N TR OL HI HO LINEAR REG. HS DRIVE LO LO TPS28255 BOOT 2 6 VDD VSS ISOLATION AND FEEDBACK VDD (4.
PAGE 4
TPS28225 TPS28226 SLUS710C – MAY 2006 – REVISED APRIL 2010 www.ti.com TYPICAL APPLICATIONS (continued) Multi-Phase Synchronous Buck Converter VDD (4.
PAGE 5
TPS28225 TPS28226 www.ti.com SLUS710C – MAY 2006 – REVISED APRIL 2010 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) TPS28225/6 Input supply voltage range, VDD VALUE UNIT (3) –0.3 to 8.8 Boot voltage, VBOOT –0.3 to 33 DC Phase voltage, VPHASE –2 to 32 or VBOOT + 0.3 – VDD whichever is less Pulse < 400 ns, E = 20 mJ –7 to 33.1 or VBOOT + 0.
PAGE 6
TPS28225 TPS28226 SLUS710C – MAY 2006 – REVISED APRIL 2010 www.ti.com ELECTRICAL CHARACTERISTICS (1) VDD = 7.2 V, EN/PG pulled up to VDD by 100-kΩ resistor, TA = TJ = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT UNDER VOLTAGE LOCKOUT Rising threshold (TPS28225) 3.2 Rising threshold (TPS28226) VPWM = 0 V Falling threshold (TPS28225) Falling threshold (TPS28226) 3.5 3.8 6.35 6.70 2.7 3.0 4.7 5.0 Hysteresis (TPS28225) V 0.5 Hysteresis (TPS28226) 1.
PAGE 7
TPS28225 TPS28226 www.ti.com SLUS710C – MAY 2006 – REVISED APRIL 2010 ELECTRICAL CHARACTERISTICS (1) (continued) VDD = 7.2 V, EN/PG pulled up to VDD by 100-kΩ resistor, TA = TJ = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LOWER GATE DRIVER OUTPUT (LGATE) tRL 2.0 Ω Source resistance 500 mA source current 1.0 Source current (3) VLGATE = 2.5 V 2.0 A Rise time (3) CL = 3 nF 10 ns Sink resistance 500 mA sink current 0.
PAGE 8
TPS28225 TPS28226 SLUS710C – MAY 2006 – REVISED APRIL 2010 www.ti.com DEVICE INFORMATION SOIC-8 Package (top view) UGATE 1 8 PHASE BOOT 2 7 EN/PG PWM 3 6 VDD GND 4 5 LGATE DRB-8 Package (top view) U G ATE 1 BOOT 2 PWM 3 GND 4 Exposed Thermal Die Pad 8 PHASE 7 EN/PG 6 VDD 5 LG A T E BLOCK DIAGRAM VDD 6 2 BOOT 1 UGATE 8 PHASE 5 LGATE 4 GND UVLO EN/PG 7 THERMAL SD HLD-OFF TIME 27K SHOOTTHROUGH PROTECTION VDD 3-STATE INPUT CIRCUIT PWM 3 13K A.
PAGE 9
TPS28225 TPS28226 www.ti.com SLUS710C – MAY 2006 – REVISED APRIL 2010 TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION SOIC-8 DRB-8 NAME 1 1 UGATE O Upper gate drive sink/source output. Connect to gate of high-side power N-Channel MOSFET. 2 2 BOOT I/O Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET.
PAGE 10
TPS28225 TPS28226 SLUS710C – MAY 2006 – REVISED APRIL 2010 www.ti.
PAGE 11
TPS28225 TPS28226 www.ti.com SLUS710C – MAY 2006 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS BIAS SUPPLY CURRENT vs TEMPERATURE (VEN/PG = Low, PWM Input Floating, VDD = 7.2V) UNDER VOLTAGE LOCKOUT THRESHOLD vs TEMPERATURE 8.00 480 7.50 UVLO − Under Voltage Lockout − V 500 IDD(off) − Bias Supply − µA 460 440 420 400 380 360 340 320 7.00 TPS28226 Rising 6.50 6.00 5.50 TPS28226 Falling 5.00 4.50 4.00 TPS28225 Rising 3.50 3.00 TPS28225 Falling 2.50 300 2.
PAGE 12
TPS28225 TPS28226 SLUS710C – MAY 2006 – REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) LGATE DC OUTPUT IMPEDANCE vs TEMPERATURE (VDD = 7.2 V) 2.00 2.00 1.75 1.75 ROUT − Output Impedance − Ω ROUT − Output Impedance − Ω UGATE DC OUTPUT IMPEDANCE vs TEMPERATURE, (VDD = 7.2 V) 1.50 RSOURCE 1.25 1.00 0.75 RSINK 0.50 0.25 1.50 1.25 1.00 RSOURCE 0.75 0.50 RSINK 0.25 0 0 −40 25 125 −40 25 TJ − Temperature − °C Figure 5. Figure 6.
PAGE 13
TPS28225 TPS28226 www.ti.com SLUS710C – MAY 2006 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) UGATE AND LGATE (Turning OFF Propagation Delays) vs TEMPERTURE (VDD = 7.2 V, CLOAD = 3 nF) UGATE AND LGATE (Dead Time) vs TEMPERTURE (VDD = 7.2 V, CLOAD = 3 nF) 20.0 30 UGATE UGATE tDTU/tDTL − UGATE and LGATE − ns tDLU/tDLL − UGATE and LGATE − ns 17.5 25 20 15 LGATE 10 5 15.0 12.5 10.0 7.5 LGATE 5.0 2.5 0.
PAGE 14
TPS28225 TPS28226 SLUS710C – MAY 2006 – REVISED APRIL 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) BIAS SUPPLY CURRENT vs SWITCHING FREQUENCY (VDD = 7.2 V, No Load, TJ = 25°C) DRIVER DISSIPATED POWER vs SWITCHING FREQUENCY (Different Load Charge, VDD = 7.
PAGE 15
TPS28225 TPS28226 www.ti.com SLUS710C – MAY 2006 – REVISED APRIL 2010 TYPICAL CHARACTERISTICS (continued) NORMAL AND 3-STATE OPERATION ENTER/EXIT CONDITIONS MINIMUM UGATE PULSE SWITCHING WAVEFORMS VDD = 7.2 V, CL = 3 nF, TJ = 25°C PWM − 2 V/div. Voltage Voltage − 5 V/div. PWM 30ns LGATE 3−St Trigger, High = 3−St UGATE − 10 V/div. UGATE LGATE − 10 V/div. t − Time − 5 µs/div. t − Time − 20 ns/div. Figure 17. Figure 18.
PAGE 16
TPS28225 TPS28226 SLUS710C – MAY 2006 – REVISED APRIL 2010 www.ti.com DETAILED DESCRIPTION Under Voltage Lockout (UVLO) The TPS28225/6 incorporates an under voltage lockout circuit that keeps the driver disabled and external power FETs in an OFF state when the input supply voltage VDD is insufficient to drive external power FETs reliably. During power up, both gate drive outputs remain low until voltage VDD reaches UVLO threshold, typically 3.5 V for the TPS28225/6 and and 6.35 V for the TPS28226.
PAGE 17
TPS28225 TPS28226 www.ti.com SLUS710C – MAY 2006 – REVISED APRIL 2010 Enable/Power Good The Enable/Power Good circuit allows the TPS28225/6 to follow the PWM input signal when the voltage at EN/PG pin is above 2.1 V maximum. This circuit has a unique two-way communication capability. This is illustrated by Figure 19. VDD = 4.5 V to 8 V for the TPS28225 or 6.8 V to 8.0 V for the TPS28226 VCC Driver TPS28225 6 System .
PAGE 18
TPS28225 TPS28226 SLUS710C – MAY 2006 – REVISED APRIL 2010 www.ti.com 3-State Input As soon as the EN/PG pin is set high and input PWM pulses are initiated (see Note below). The dead-time control circuit ensures that there is no overlapping between UGATE and LGATE drive outputs to eliminate shoot through current through the external power FETs. Additionally to operate under periodical pulse sequencing, the TPS28225/6 has a self-adjustable PWM 3-state input circuit.
PAGE 19
TPS28225 TPS28226 www.ti.com SLUS710C – MAY 2006 – REVISED APRIL 2010 IMPORTANT NOTE: Any external resistor between PWM input and GND with the value lower than 40kΩ can interfere with the 3-state thresholds. If the driver is intended to operate in the 3-state mode, any resistor below 40kΩ at the PWM and GND should be avoided. A resistor lower than 3.5kΩ connected between the PWM and GND completely disables the 3-state function.
PAGE 20
TPS28225 TPS28226 SLUS710C – MAY 2006 – REVISED APRIL 2010 www.ti.com Bootstrap Diode The bootstrap diode provides the supply voltage for the UGATE driver by charging the bootstrap capacitor connected between BOOT and PHASE pins from the input voltage VDD when the low-side FET is in ON state. At the very initial stage when both power FETs are OFF, the bootstrap capacitor is pre-charged through this path including the PHASE pin, output inductor and large output capacitor down to GND.
PAGE 21
TPS28225 TPS28226 www.ti.com SLUS710C – MAY 2006 – REVISED APRIL 2010 APPLICATION INFORMATION Switching The MOSFETs Driving the MOSFETs efficiently at high switching frequencies requires special attention to layout and the reduction of parasitic inductances. Efforts need to be done both at the driver’s die and package level and at the PCB layout level to keep the parasitic inductances as low as possible.
PAGE 22
TPS28225 TPS28226 SLUS710C – MAY 2006 – REVISED APRIL 2010 www.ti.com Voltage LGATE Falling, V or A LGATE Falling, V or A The ISOURCE current charges the gate capacitor and the ISINK current discharges it. The rise and fall time of voltage across the gate defines how quickly the MOSFET can be switched. The timing parameters specified in datasheet for both upper and lower driver are shown in Figure 15 and Figure 16 where 3-nF load capacitor has been used for the characterization data.
PAGE 23
TPS28225 TPS28226 www.ti.com SLUS710C – MAY 2006 – REVISED APRIL 2010 Turning Off of the MOSFET needs to be done as fast as possible to reduce switching losses. For this reason the TPS28225/6 driver has very low output impedance specified as 0.4Ω typ for lower driver and 1Ω typ for upper driver at dc current. Assuming 8-V drive voltage and no parasitic inductances, one can expect an initial sink current amplitude of 20A and 8A respectively for the lower and upper drivers.
PAGE 24
TPS28225 TPS28226 SLUS710C – MAY 2006 – REVISED APRIL 2010 www.ti.com The schematic of one of the phases in a multi-phase synchronous buck regulator and the related layout are shown in Figure 27 and Figure 28. These help to illustrate good design practices. The power stage includes one high-side MOSFET Q10 and two low-side MOSFETS (Q8 and Q9). The driver (U7) is located on bottom side of PCB close to the power MOSFETs.
PAGE 25
TPS28225 TPS28226 www.ti.com SLUS710C – MAY 2006 – REVISED APRIL 2010 Figure 30. Phase Falling Edge Switching Waveforms (10ns/div) of the Power State in Figure 27 List of Materials The list of materials for this specific example is provided in the table. The component vendors are not limited to those shown in the table below. It should be notd that, in this example, the power MOSFET packages were chosen with drains on top. The decoupling capacitors C47, C48, C65, and C66 were chosen to have low profiles.
PAGE 26
TPS28225 TPS28226 SLUS710C – MAY 2006 – REVISED APRIL 2010 www.ti.com Efficiency of Power Stage vs Load Current at Different Switching Frequencies Efficiency achieved using TPS28225/6 driver with 8-V drive at different switching frequencies a similar industry 5-V driver using the power stage in Figure 27 is shown in Figure 33, Figure 35, Figure 34, Figure 31 and Figure 32.
PAGE 27
TPS28225 TPS28226 www.ti.com SLUS710C – MAY 2006 – REVISED APRIL 2010 EFFICIENCY vs LOAD CURRENT EFFICIENCY vs LOAD CURRENT 90 90 TI: 700kHz Ind: 700kHz TI: 800kHz Ind: 800kHz Efficiency − % 85 Efficiency − % 85 80 80 75 75 5 10 15 20 25 30 35 5 10 15 CL − Load Currnt − A 20 25 30 35 CL − Load Currnt − A Figure 34. Figure 35. When using the same power stage, the driver with the optimal drive voltage and optimal dead time can boost efficiency up to 5%.
PAGE 28
TPS28225 TPS28226 SLUS710C – MAY 2006 – REVISED APRIL 2010 www.ti.com The plots show that the RDS(on) at 5-V drive is substantially larger than at 7 V and above that the RDS(on) curve is almost flat. This means that moving from 5-V drive to an 8-V drive boosts the efficiency because of lower RDS(on) of the MOSFETs at 8 V. Further increase of drive voltage from 8 V to 12 V only slightly decreases the conduction losses but the power dissipated inside the driver increases dramatically (by 125%).
PAGE 29
PACKAGE OPTION ADDENDUM www.ti.
PAGE 30
PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
PAGE 31
PACKAGE MATERIALS INFORMATION www.ti.com 30-May-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS28225DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS28225DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS28225DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.
PAGE 32
PACKAGE MATERIALS INFORMATION www.ti.com 30-May-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS28225DR SOIC D 8 2500 340.5 338.1 20.6 TPS28225DRBR SON DRB 8 3000 367.0 367.0 35.0 TPS28225DRBT SON DRB 8 250 210.0 185.0 35.0 TPS28225DRBT SON DRB 8 250 210.0 185.0 35.0 TPS28226DR SOIC D 8 2500 340.5 338.1 20.6 TPS28226DRBR SON DRB 8 3000 367.0 367.0 35.
PAGE 33
PAGE 34
PAGE 35
PAGE 36
PAGE 37
PAGE 38
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.