Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - gate drivers Non-inverting High side, Low side, Sychronous SOIC 8

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SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Floating Bootstrap or Ground-Reference

High-Side Driver

D Adaptive Dead-Time Control

D 50-ns Max Rise/Fall Times With 3.3-nF Load

D 2.4-A Typical Output Current

D 4.5-V to 15-V Supply Voltage Range

D TTL-Compatible Inputs

D Internal Schottky Bootstrap Diode

D Low Supply Current....3 mA Typical

D Ideal for High-Current Single or Multiphase

Power Supplies

D −40°C to 125°C Operating Virtual

Junction-Temperature Range

description

The TPS2836 and TPS2837 are MOSFET drivers for synchronous-buck power stages. These devices are ideal

for designing a high-performance power supply using switching controllers that do not have MOSFET drivers.

The drivers are designed to deliver minimum 2-A peak currents into large capacitive loads. The high-side driver

can be configured as ground-reference or as floating-bootstrap. An adaptive dead-time control circuit eliminates

shoot-through currents through the main power FETs during switching transitions and provides high efficiency

for the buck regulator.

The TPS2836 has a noninverting input, while the TPS2837 has an inverting input. These drivers, available in

8-terminal SOIC packages, operate over a junction temperature range of − 40°C to 125°C.

AVAILABLE OPTIONS

PACKAGED DEVICES

SOIC

(D)

−40°C to 125°C

TPS2836D

TPS2837D

The D package is available taped and reeled. Add R

suffix to device type (e.g., TPS2836DR)

Related Synchronous MOS FET Drivers

DEVICE NAME ADDITIONAL FEATURES INPUTS

TPS2830

ENABLE, SYNC and CROWBAR

CMOS

Noninverted

TPS2831

ENABLE, SYNC and CROWBAR CMOS

Inverted

TPS2832

W/O ENABLE, SYNC and CROWBAR

CMOS

Noninverted

TPS2833

W/O ENABLE, SYNC and CROWBAR CMOS

Inverted

TPS2834

ENABLE, SYNC and CROWBAR

TTL

Noninverted

TPS2835

ENABLE, SYNC and CROWBAR TTL

Inverted

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

D PACKAGE

(TOP VIEW)

PGND

BOOT

HIGHDR

BOOTLO

LOWDR

Summary of content (17 pages)

PAGE 1
SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002 D Floating Bootstrap or Ground-Reference D D D D D D D D D D PACKAGE (TOP VIEW) High-Side Driver Adaptive Dead-Time Control 50-ns Max Rise/Fall Times With 3.3-nF Load 2.4-A Typical Output Current 4.5-V to 15-V Supply Voltage Range TTL-Compatible Inputs Internal Schottky Bootstrap Diode Low Supply Current....
PAGE 2
SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002 functional block diagram 4 8 VCC BOOT 1 MΩ 7 (TPS2836 Only) HIGHDR 250 kΩ 6 BOOTLO 1 IN VCC (TPS2837 Only) 5 LOWDR 250 kΩ 2 3 PGND DT Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION BOOT 8 I Bootstrap terminal. A ceramic capacitor is connected between BOOT and BOOTLO to develop the floating bootstrap voltage for the high-side MOSFET.
PAGE 3
SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002 detailed description low-side driver The low-side driver is designed to drive low rDS(on) N-channel MOSFETs. The current rating of the driver is 2 A, source and sink. high-side driver The high-side driver is designed to drive low rDS(on) N-channel MOSFETs. The current rating of the driver is 2 A, source and sink.
PAGE 4
SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002 electrical characteristics over recommended operating virtual junction temperature range, VCC = 6.5 V, CL = 3.3 nF (unless otherwise noted) supply current PARAMETER TEST CONDITIONS Supply voltage range TYP 4.
PAGE 5
SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002 electrical characteristics over recommended operating virtual junction temperature range, VCC = 6.5 V, CL = 3.3 nF (unless otherwise noted) (continued) dead-time PARAMETER VIH VIL High-level input voltage VIH VIL High-level input voltage Low-level input voltage Low-level input voltage TEST CONDITIONS LOWDR Over the VCC range (see Note 3) DT Over the VCC range MIN TYP MAX UNIT 0.
PAGE 6
SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002 TYPICAL CHARACTERISTICS FALL TIME vs SUPPLY VOLTAGE RISE TIME vs SUPPLY VOLTAGE 50 50 CL = 3.3 nF TJ = 25°C 45 40 40 t f − Fall Time − ns t r − Rise Time − ns CL = 3.3 nF TJ = 25°C 45 High Side 35 30 Low Side 25 35 High Side 30 25 20 20 15 15 10 Low Side 10 4 5 6 7 9 10 11 12 13 8 VCC − Supply Voltage − V 14 15 4 5 6 Figure 1 VCC = 6.5 V CL = 3.
PAGE 7
SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002 TYPICAL CHARACTERISTICS HIGH-TO-LOW PROPAGATION DELAY TIME vs SUPPLY VOLTAGE, HIGH TO LOW LEVEL 150 t PHL − High-to-Low Propagation Delay Time − ns t PLH − Low-to-High Propagation Delay Time − ns LOW-TO-HIGH PROPAGATION DELAY TIME vs SUPPLY VOLTAGE, LOW TO HIGH LEVEL CL = 3.
PAGE 8
SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002 TYPICAL CHARACTERISTICS DRIVER-OUTPUT FALL TIME vs LOAD CAPACITANCE DRIVER-OUTPUT RISE TIME vs LOAD CAPACITANCE 1000 1000 VCC = 6.5 V TJ = 27°C t f − Fall Time − ns t r − Rise Time − ns VCC = 6.5 V TJ = 27°C 100 High Side Low Side 10 1 0.01 1 0.1 10 100 High Side Low Side 10 1 0.
PAGE 9
SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002 TYPICAL CHARACTERISTICS PEAK SOURCE CURRENT vs SUPPLY VOLTAGE PEAK SINK CURRENT vs SUPPLY VOLTAGE 4 4 TJ = 25°C TJ = 25°C 3.5 3 3 Low Side Peak Sink Current − A Peak Source Current − A 3.5 2.5 2 High Side 1.5 Low Side 2.5 2 High Side 1.5 1 1 0.5 0.
PAGE 10
SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002 APPLICATION INFORMATION Figure 17 shows the circuit schematic of a 100-kHz synchronous-buck converter implemented with a TL5001A pulse-width-modulation (PWM) controller and a TPS2837 driver. The converter operates over an input range from 4.5 V to 12 V and has a 3.3-V output. The circuit can supply 3 A continuous load and the transient load is 5 A.
PAGE 11
SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002 APPLICATION INFORMATION Great care should be taken when laying out the PC board. The power-processing section is the most critical and will generate large amounts of EMI if not properly configured. The junction of Q1, Q2, and L1 should be very tight.
PAGE 12
SLVS224B − NOVEMBER 1999 − REVISED AUGUST 2002 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°−ā 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.
PAGE 13
PACKAGE OPTION ADDENDUM www.ti.
PAGE 14
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS2836DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS2837DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.
PAGE 16
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2836DR SOIC D 8 2500 340.5 338.1 20.6 TPS2837DR SOIC D 8 2500 340.5 338.1 20.
PAGE 17
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