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

   

SLVS312A – JULY 2000 – REVISED DECEMBER 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Overvoltage Protection and Lockout for

12 V, 5 V, 3.3 V

D Undervoltage Protection and Lockout for

5 V and 3.3 V

D Fault Protection Output With Open-Drain

Output Stage

D Open-Drain Power Good Output Signal for

Power Good Input, 3.3 V and 5 V

D Power Good Delay; 300-ms TPS3510,

150-ms TPS3511

D 75-ms Delay for 5-V and 3.3-V Power

Supply Short-Circuit Turnon Protection

D 2.3-ms PSON Control to FPO Turnoff Delay

D 38-ms PSON Control Debounce

D 73-µs Width Noise Deglitches

D Wide Supply Voltage Range From 4 V

to 15 V

description

The TPS3510/1 is designed to minimize external components of personal-computer switching power supply

systems. It provides protection circuits, power good indicator, fault protection output (FPO

) and PSON control.

Overvoltage protection (OVP) monitors 3.3 V, 5 V, and 12 V (12-V signal detects via V

pin). Undervoltage

protection (UVP) monitors 3.3 V and 5 V. When an OV or UV condition is detected, the power good output (PGO)

is set to low and FPO

is latched high. PSON from low to high resets the protection latch. UVP function is enabled

75 ms after PSON

is set low and debounced. Furthermore, there is a 2.3-ms delay (and an additional 38-ms

debounce) at turnoff. There is no delay during turnon.

Power good feature monitors PGI, 3.3 V and 5 V and issues a power good signal when the output is ready.

The TPS3510/1 is characterized for operation from –40°C to 85°C.

typical application

PGI

GND

FPO

PSON

PGO

VS5

VS33

PSON

(From Motherboard)

5 V

PGO

0.5 V

Drop

PGI

12 V

5 V

3.3 V

        

         

       

   

        

         

       

   

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PGI

GND

FPO

PSON

PGO

VS5

VS33

D OR P PACKAGE

(TOP VIEW)

Summary of content (18 pages)

PAGE 1
SLVS312A – JULY 2000 – REVISED DECEMBER 2002 D Overvoltage Protection and Lockout for D D D D D D D D D D OR P PACKAGE (TOP VIEW) 12 V, 5 V, 3.3 V Undervoltage Protection and Lockout for 5 V and 3.3 V Fault Protection Output With Open-Drain Output Stage Open-Drain Power Good Output Signal for Power Good Input, 3.3 V and 5 V Power Good Delay; 300-ms TPS3510, 150-ms TPS3511 75-ms Delay for 5-V and 3.3-V Power Supply Short-Circuit Turnon Protection 2.
PAGE 2
SLVS312A – JULY 2000 – REVISED DECEMBER 2002 FUNCTION TABLE PGI PSON UV CONDITION (3.3 V OR 5 V) <0.95 V L no <0.95 V L no OV CONDITION (3.3 V, 5 V, OR 12 V) FPO PGO no L L yes H L <0.95 V L yes no L L 0.95 V 1.15 V L no no L H PGI > 1.15 V L no yes H L PGI > 1.
PAGE 3
SLVS312A – JULY 2000 – REVISED DECEMBER 2002 functional block diagram VDD 12 V OV + _ POR VS5 R 5 V OV + _ S 73-µs Debounce FPO Q VS33 2.3-ms Delay 73-µs Debounce VDD 3.3 V OV 38-ms Debounce + _ 3.3 V UV + _ 75-ms Delay VDD 5 V UV + _ + _ PGO PGI1 Band-Gap Reference 1.15 V PGI PSON 150-µs Debounce Delay† PGI2 + _ 150-µs Debounce and 4.8-ms Delay Band-Gap Reference 0.
PAGE 4
SLVS312A – JULY 2000 – REVISED DECEMBER 2002 timing diagram VDD PSON FPO PGI 3.3 V, 5 V 12 V PGO td1 td1 tb PG OFF Delay td1 td2 Protect Occur PSON On PSON On PSON Off Terminal Functions TERMINAL 4 NAME NO.
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SLVS312A – JULY 2000 – REVISED DECEMBER 2002 detailed description power good and power good delay A PC power supply is commonly designed to provide a power-good signal, which is defined by the computer manufacturers. PGO is a power-good signal and should be asserted high by the PC power supply to indicate that the 5-V and 3.3-V outputs are above the under-voltage threshold limit.
PAGE 6
SLVS312A – JULY 2000 – REVISED DECEMBER 2002 power supply remote on/off (PSON) and fault protect output (FPO)(continued) When the FPO signal is held high due to an occurring fault condition, the fault status is latched and the outputs of the main power rails should not deliver current but are held at 0 V. Toggling the power supply remote on/off (PSON) from low to high resets the fault-protection latch.
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SLVS312A – JULY 2000 – REVISED DECEMBER 2002 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, VDD (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V Output voltage VO: FPO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V PGO . . . . .
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SLVS312A – JULY 2000 – REVISED DECEMBER 2002 electrical characteristics over recommended operating conditions (unless otherwise noted) overvoltage protection PARAMETER TEST CONDITIONS Overvoltage threshold ILKG VOL MIN TYP MAX VS33 3.7 3.9 4.1 VS5 5.7 6.1 6.5 VDD 13.2 13.8 14.4 Leakage current (FPO) V(FPO) = 5 V Low-level output voltage (FPO) VDD = 5 V, VDD = 5 V Noise deglitch time OVP 5 Isink = 20 mA UNIT V µA 0.
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SLVS312A – JULY 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE INPUT CURRENT (PSON) vs INPUT VOLTAGE (PSON) 400 20 VDD = 4 V TA = –40°C 0 TA = 85°C TA = 25°C 200 I I – Input Current – µ A I DD – Supply Current – µ A 300 100 TA = 0°C 0 –100 –20 –40 –60 –80 TA = –40°C TA = 0°C TA = 25°C TA = 85°C –100 –200 PGI = 1.4 V PSON = 5 V –120 –300 0 2.5 5 10 7.5 12.
PAGE 10
SLVS312A – JULY 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT VOLTAGE (PGO) vs LOW-LEVEL OUTPUT CURRENT (PGO) LOW-LEVEL OUTPUT VOLTAGE (PGO) vs LOW-LEVEL OUTPUT CURRENT (PGO) 4 600 VOL – Low-Level Output Voltage – mV VOL – Low-Level Output Voltage – V VDD = 4 V PSON = GND TA = 85°C 3 2 TA = –40°C TA = 25°C 1 TA = 0°C 0 0 25 50 75 100 125 IOL – Low-Level Output Current – mA VDD = 4 V PSON = GND Exploded View 500 400 TA = 85°C 300
PAGE 11
PACKAGE OPTION ADDENDUM www.ti.
PAGE 12
PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS3510DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TPS3511DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS3510DR SOIC D 8 2500 340.5 338.1 20.6 TPS3511DR SOIC D 8 2500 340.5 338.1 20.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.