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SLVS340D − DECEMBER 2000 − REVISED JULY 2008

  

  



FEATURES

D Supply Current of 40 µA (Max)

D Battery Supply Current of 100 nA (Max)

D Supply Voltage Supervision Range:

− Adjustable

− Other Versions Available on Request

D Backup-Battery Voltage Can Exceed V

D Power-On Reset Generator With Fixed 100-ms

Reset Delay Time

D Active-High and Active-Low Reset Output

D Chip-Enable Gating: 3 ns (at V

= 5 V) Max

Propagation Delay

D 10-Pin MSOP Package

D Temperature Range: −40°C to 85°C

APPLICATIONS

D Fax Machines

D Set-Top Boxes

D Advanced Voice Mail Systems

D Portable Battery-Powered Equipment

D Computer Equipment

D Advanced Modems

D Automotive Systems

D Portable Long-Time Monitoring Equipment

D Point-of-Sale Equipment

DESCRIPTION

The TPS3613-01 supervisory circuit monitors and controls

processor activity by providing backup-battery switchover

for data retention of CMOS RAM.

During power-on, reset (RESET and RESET

) is asserted

when the supply voltage (V

or V

BAT

) becomes higher

than 1.1 V.

Thereafter, the supply voltage supervisor monitors V

the SENSE pin through external feedback resistors and

keeps reset active as long as SENSE remains below the

threshold voltage, V

An internal timer delays the release of the reset state to

ensure proper system reset. The delay time starts after

SENSE rises above the threshold voltage, V

When SENSE drops below V

, reset becomes active

again.

The TPS3613-01 is available in a 10-pin MSOP package

and is characterized for operation over a temperature

range of −40

°C to +85°C.

CEIN CEOUT

BAT

SENSE

Backup

Battery

RESET

OUT

GND

Manual

Reset

0.1

Power

Supply

Address Bus

GND

RESET

Data Bus

Address

Decoder

Switchover

Capacitor

0.1

TPS3613

CMOS

RAM

CMOS

RAM

Real−

Time

Clock

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (19 pages)

PAGE 1
www.ti.com SLVS340D − DECEMBER 2000 − REVISED JULY 2008 FEATURES D Supply Current of 40 µA (Max) D Battery Supply Current of 100 nA (Max) D Supply Voltage Supervision Range: DESCRIPTION The TPS3613-01 supervisory circuit monitors and controls processor activity by providing backup-battery switchover for data retention of CMOS RAM.
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www.ti.com SLVS340D − DECEMBER 2000 − REVISED JULY 2008 PACKAGE INFORMATION TA DEVICE NAME −40°C to +85°C TPS3613−01DGSR† † The DGSR passive indicates tape and reel of 2500 parts. MARKING AFK ordering information application specific versions TPS361 3 − 01 DGS R NOMINAL VOLTAGE‡, VNOM DEVICE NAME Adjustable TPS3613−01 DGS ‡ For other threshold voltages, contact the local TI sales office for availability and lead-time.
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www.ti.com SLVS340D − DECEMBER 2000 − REVISED JULY 2008 FUNCTIONAL SCHEMATIC TPS3613 VBAT + _ Switch Control VOUT VDD R MR + _ SENSE RESET Logic + Timer Reference Voltage or 1.15 V RESET RESET VOUT CEIN CEOUT Terminal Functions TERMINAL NAME I/O DESCRIPTION NO.
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www.ti.com SLVS340D − DECEMBER 2000 − REVISED JULY 2008 TIMING DIAGRAM VDD VDD VBAT 1.1V t SENSE VIT VOUT t RESET t td td td t MR td t NOTE: Shaded area in RESET is undefined.
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www.ti.com SLVS340D − DECEMBER 2000 − REVISED JULY 2008 detailed description backup-battery switchover supervisors do not connect VBAT to VOUT when VBAT is greater than VDD. VBAT only connects to VOUT (through a 15-Ω switch) when VDD falls below VIT and VBAT is greater than VDD. When VDD recovers, switchover is deferred either until VDD crosses VBAT, or when VDD rises above the reset threshold VIT. VOUT connects to VDD through a 1-Ω (max) PMOS switch when VDD crosses the reset threshold.
PAGE 6
www.ti.com SLVS340D − DECEMBER 2000 − REVISED JULY 2008 detailed description (continued) chip-enable signal gating The internal gating of chip-enable (CE) signals prevents erroneous data from corrupting CMOS RAM during an under-voltage condition. The TPS3613 uses a series transmission gate from CEIN to CEOUT. During normal operation (reset not asserted), the CE transmission gate is enabled and passes all CE transitions.
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www.ti.com SLVS340D − DECEMBER 2000 − REVISED JULY 2008 ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE (unless otherwise noted)(1) Supply voltage: VDD(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V MR and SENSE pins(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to (VDD + 0.3 V) Continuous output current at VOUT: IO . . . . . . . . . . . . . . . . . . .
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www.ti.com SLVS340D − DECEMBER 2000 − REVISED JULY 2008 ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING CONDITIONS (unless otherwise noted) PARAMETER TEST CONDITIONS VDD − 0.2 V IOH = −20 µA IOH = −80 µA IOH = −120 µA IOH = −1 mA VDD − 0.3 V CEOUT VDD = 1.8 V, VDD = 3.3 V, VDD = 5 V, VOUT = 1.8 V, Enable mode CEIN = VOUT VOUT = 3.3 V, IOH = −2 mA VOUT = 5 V, IOH = −5 mA VOUT − 0.3 V CEOUT Disable mode VOUT = 3.3 V, IOH = −0.5 mA VOUT − 0.
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www.ti.com SLVS340D − DECEMBER 2000 − REVISED JULY 2008 TIMING REQUIREMENTS AT RL = 1 MΩ, CL = 50 PF, TA = −40°C TO +85°C PARAMETER tw Pulse width TEST CONDITIONS SENSE VIH = VIT + 0.2 V, VIL = VIT − 0.2 V MIN TYP MAX UNIT µs 6 SWITCHING CHARACTERISTICS AT RL = 1 MΩ, CL= 50 PF, TA = −40°C TO +85°C PARAMETER td Delay time tPLH Propagation (delay) time, low-to-high-level output VSENSE ≥ VIT + 0.2 V, MR ≥ 0.
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www.ti.com SLVS340D − DECEMBER 2000 − REVISED JULY 2008 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE 30 40 35 I DD − Supply Current − µ A TA = 25°C 30 25 20 TA = 0°C 15 TA = −40°C 10 20 VDD Mode VBAT = GND or TA = 25°C TA = 0°C TA = 85°C 15 TA = −40°C 10 5 ICEOUT = 5 mA VDD = 5 V 5 VBAT Mode VBAT = 2.
PAGE 12
www.ti.com SLVS340D − DECEMBER 2000 − REVISED JULY 2008 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE AT RESET vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE AT RESET vs HIGH-LEVEL OUTPUT CURRENT 5.1 VDD = 5 V VBAT = GND VOH − High-Level Output Voltage at RESET − V VOH − High-Level Output Voltage at RESET − V 6 5 TA = −40°C TA = 25°C 4 TA = 0°C 3 2 TA = 85°C 1 0 −35 −30 −25 −20 −15 −10 −5 IOH − High-Level Output Current − mA Expanded View 5 TA = −40°C 4.9 4.8 4.
PAGE 13
www.ti.com SLVS340D − DECEMBER 2000 − REVISED JULY 2008 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE AT CEOUT vs HIGH-LEVEL OUTPUT CURRENT 3.5 3.5 3 VOH − High-Level Output Voltage at CEOUT − V VOH − High-Level Output Voltage at CEOUT − V HIGH-LEVEL OUTPUT VOLTAGE AT CEOUT vs HIGH-LEVEL OUTPUT CURRENT TA = −40°C 2.5 TA = 25°C TA = 0°C 2 1.5 TA = 85°C 1 Disable Mode V(CEIN) = Open VDD = 1.65 V 0.5 0 −4.5 −4 −3.5 −3 −2.5 −2 −1.5 −1 −0.5 0 V(CEIN) = Open VDD = 1.65 V 3.4 3.
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www.ti.com SLVS340D − DECEMBER 2000 − REVISED JULY 2008 TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT VOLTAGE AT CEOUT vs LOW-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT VOLTAGE AT CEOUT vs LOW-LEVEL OUTPUT CURRENT VOL− Low-Level Output Voltage at CEOUT − mV VOL− Low-Level Output Voltage at CEOUT − V 3.5 Enable Mode V(CEIN) = GND VDD = 5 V 3 2.5 TA = 85°C 2 TA = 25°C TA = 0°C 1.5 TA = −40°C 1 0.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 16
PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS3613-01DGSR Package Package Pins Type Drawing MSOP DGS 10 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 5.3 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.
PAGE 17
PACKAGE MATERIALS INFORMATION www.ti.com 17-Apr-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS3613-01DGSR MSOP DGS 10 2500 358.0 335.0 35.
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