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RESET

GND

DBV (SOT-23) PACKAGE

(TOP VIEW)

1.2 V 3.3 V

TPS3808G12 TPS3808G33 DSP

SENSE V

SENSE

I/O

CORE

GPIO

GNDGNDGND

RESET

GND

SENSE

DRV PACKAGE

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SENSE

TPS3808-Q1

www.ti.com

SBVS085H –JANUARY 2007–REVISED JUNE 2012

LOW-QUIESCENT-CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT

Check for Samples: TPS3808-Q1

FEATURES

DESCRIPTION

• Qualified for Automotive Applications

The TPS3808 microprocessor supervisory circuits

• Power-On Reset Generator With Adjustable

monitor system voltages from 0.4 V to 5 V, asserting

Delay Time: 1.25 ms to 10 s

an open-drain RESET signal when the SENSE

• Very Low Quiescent Current: 2.4 μA Typ

voltage drops below a preset threshold or when the

manual reset (MR) pin drops to a logic low. The

• High Threshold Accuracy: 0.5% Typ

RESET output remains low for the user-adjustable

• Fixed Threshold Voltages for Standard Voltage

delay time after the SENSE voltage and MR return

Rails From 1.2 V to 5 V and Adjustable Voltage

above their thresholds.

Down to 0.4 V Are Available

The TPS3808 uses a precision reference to achieve

• Manual Reset (MR) Input

0.5% threshold accuracy for V

≤ 3.3 V. The reset

• Open-Drain RESET Output

delay time can be set to 20 ms by disconnecting the

pin, 300 ms by connecting the C

pin to V

using

• Temperature Range: –40°C to 125°C

a resistor, or can be user adjusted between 1.25 ms

• Small SOT-23 Package

and 10 s by connecting the C

pin to an external

capacitor. The TPS3808 has a very low typical

APPLICATIONS

quiescent current of 2.4 μA, so it is well suited to

battery-powered applications. It is available in a small

• DSP or Microcontroller Applications

SOT-23 package and is fully specified over a

• Notebook/Desktop Computers

temperature range of –40°C to 125°C (T

• PDAs/Hand-Held Products

<br/>

• Portable/Battery-Powered Products

<br/>

• FPGA/ASIC Applications

<br/>

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (20 pages)

PAGE 1
TPS3808-Q1 www.ti.com SBVS085H – JANUARY 2007 – REVISED JUNE 2012 LOW-QUIESCENT-CURRENT PROGRAMMABLE-DELAY SUPERVISORY CIRCUIT Check for Samples: TPS3808-Q1 FEATURES 1 • • • • • • • • • DESCRIPTION Qualified for Automotive Applications Power-On Reset Generator With Adjustable Delay Time: 1.25 ms to 10 s Very Low Quiescent Current: 2.4 μA Typ High Threshold Accuracy: 0.5% Typ Fixed Threshold Voltages for Standard Voltage Rails From 1.2 V to 5 V and Adjustable Voltage Down to 0.
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TPS3808-Q1 SBVS085H – JANUARY 2007 – REVISED JUNE 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
TPS3808-Q1 www.ti.com SBVS085H – JANUARY 2007 – REVISED JUNE 2012 ELECTRICAL CHARACTERISTICS 1.8 V ≤ VDD ≤ 6.5 V, RLRESET = 100 kΩ, CLRESET = 50 pF, over operating temperature range (TJ = –40°C to 125°C) (unless otherwise noted), typical values at TJ = 25°C PARAMETER VDD Input supply range IDD Supply current (into VDD pin) VOL Low-level output voltage Power-up reset voltage (1) TEST CONDITIONS 6.5 2.4 5 VDD = 6.5 V, RESET not asserted, MR, RESET, CT open 2.7 6 1.3 V ≤ VDD < 1.8 V, IOL = 0.
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TPS3808-Q1 SBVS085H – JANUARY 2007 – REVISED JUNE 2012 www.ti.com FUNCTIONAL BLOCK DIAGRAMS Adjustable-Voltage Version Fixed-Voltage Versions VDD VDD VDD VDD 90k RESET MR RESET SENSE Reset Logic Timer SENSE 90k MR Reset Logic Timer R1 − − CT + CT + R2 0.4 V VREF 0.
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TPS3808-Q1 www.ti.com SBVS085H – JANUARY 2007 – REVISED JUNE 2012 VDD 0.8V 0.0V RESET tD = Reset Delay tD tD tD = Undefined State SENSE VIT + VHYS VIT MR 0.7VDD 0.3VDD Time Figure 1.
PAGE 6
TPS3808-Q1 SBVS085H – JANUARY 2007 – REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS At TJ = 25°C, VDD = 3.3 V, RLRESET = 100 kΩ, and CLRESET = 50 pF (unless otherwise noted) SUPPLY CURRENT vs SUPPLY VOLTAGE RESET TIMEOUT PERIOD vs CT 4.0 100 3.5 IDD (µA) RESET Timeout (sec) 125_ C 3.0 85_ C 2.5 2.0 25_C 1.5 1.0 10 −40°C, 25°C, 125°C 1 0.1 0.01 − 40_ C 0.5 0 0 1 2 3 4 5 6 0.001 0.0001 7 0.001 0.
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TPS3808-Q1 www.ti.com SBVS085H – JANUARY 2007 – REVISED JUNE 2012 TYPICAL CHARACTERISTICS (continued) At TJ = 25°C, VDD = 3.3 V, RLRESET = 100 kΩ, and CLRESET = 50 pF (unless otherwise noted) NORMALIZED SENSE THRESHOLD VOLTAGE (VIT) vs TEMPERATURE LOW-LEVEL RESET VOLTAGE vs RESET CURRENT 4.5 VOL Low−Level RESET Voltage (V) 1.0 0.8 Normalized VIT (%) 0.6 0.4 0.2 0 −0.2 −0.4 −0.6 −0.8 4.0 3.5 3.0 2.5 2.0 1.0 0.5 −1.0 −50 VDD = 1.8 V 1.5 0 −30 −10 10 30 50 70 90 110 130 0 0.5 1.
PAGE 8
TPS3808-Q1 SBVS085H – JANUARY 2007 – REVISED JUNE 2012 www.ti.com DEVICE OPERATION The TPS3808 microprocessor supervisory product family is designed to assert a RESET signal when either the SENSE pin voltage drops below VIT or the manual reset (MR) is driven low. The RESET output remains asserted for a user-adjustable time after both the manual reset (MR) and SENSE voltages return above the respective thresholds.
PAGE 9
TPS3808-Q1 www.ti.com SBVS085H – JANUARY 2007 – REVISED JUNE 2012 3.3V V DD SENSE 90kΩ CT TP S38 08xx x G ND Figure 11. Using an External MOSFET to Minimize IDD When MR Signal Does Not Go to VDD Selecting the Reset Delay Time The TPS3808 has three options for setting the RESET delay time as shown in Figure 12. Figure 12a shows the configuration for a fixed 300-ms typical delay time by tying CT to VDD; a resistor from 40 kΩ to 200 kΩ must be used.
PAGE 10
TPS3808-Q1 SBVS085H – JANUARY 2007 – REVISED JUNE 2012 www.ti.com REVISION HISTORY Changes from Revision G (November, 2010) to Revision H • 10 Page Changed ISENSE from µA to nA ..............................................................................................................................................
PAGE 11
PACKAGE OPTION ADDENDUM www.ti.
PAGE 12
PACKAGE OPTION ADDENDUM www.ti.com (3) 11-Apr-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPS3808G01QDBVRQ1 SOT-23 DBV 6 3000 179.0 8.4 TPS3808G01QDRVRQ1 SON B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.2 3.2 1.4 4.0 8.0 Q3 DRV 6 3000 180.0 8.4 2.3 2.3 1.15 4.0 8.0 Q2 TPS3808G125QDBVRQ1 SOT-23 DBV 6 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS3808G01QDBVRQ1 SOT-23 DBV 6 3000 203.0 203.0 35.0 TPS3808G01QDRVRQ1 SON DRV 6 3000 210.0 185.0 35.0 TPS3808G125QDBVRQ1 SOT-23 DBV 6 3000 203.0 203.0 35.0 TPS3808G12QDBVRQ1 SOT-23 DBV 6 3000 203.0 203.0 35.0 TPS3808G15QDBVRQ1 SOT-23 DBV 6 3000 203.0 203.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.